Patent Assignment
Reel/Frame 023075/0361
Change of Name
Recorded: 2009-08-11
Received: 2009-08-11
Pages: 7
Assignor
LSI LOGIC CORPORATION
Executed: 2007-04-05
Assignee
LSI CORPORATION
1621BARBER LANE, MS: D-105 LEGAL, MILPITAS, CA, 95035, UNITED STATES
Covered Properties
(6)
Small Pixel for Image Sensors with Jfet and Vertically Integrated Reset Diode
Application:
12/153,140 →
Two Layer Substrate Ball Grid Array Design
Application:
11/205,364 →
Pbga Electrical Noise Isolation of Signal Traces
Application:
10/387,261 →
Integrated Circuit Package Substrate with High Density Routing Mechanism
Application:
10/105,863 →
Tape Design to Reduce Warpage
Application:
09/894,718 →
Layout of Vdd and Vss Balls in a Four Layer Pbga
Application:
09/781,866 →