Bonding of laminates with electrical interconnects
A microelectronic assembly including first and second laminated microelectronic elements is provided. A patterned bonding layer is disposed on a face of each of the first and second laminated microelectronic elements. The patterned bonding layers are mechanically and electrically bonded to form the microelectronic assembly.
1. A method of forming a microelectronic assembly, comprising:
forming a first patterned bonding layer at a first face of a first laminated multilayer microelectronic element, the first laminated multilayer microelectronic element comprising a plurality of alternating conductive and insulating layers disposed on opposite surfaces of a core layer;
coupling a first plurality of conductive bonding portions of the first patterned bonding layer to a plurality of first element contacts at the first face of the first laminated multilayer microelectronic element;
forming a second patterned bonding layer at a second face of a second laminated multilayer microelectronic element, the second laminated multilayer microelectronic element comprising another plurality of alternating conductive and insulating layers disposed on opposite surfaces of a core layer;
coupling a second plurality of conductive bonding portions of the second patterned bonding layer to a plurality of second element contacts at the second face of the second laminated multilayer microelectronic element, the plurality of second element contacts facing the plurality of first element contacts;
mechanically and electrically bonding the second patterned bonding layer to the first patterned bonding layer, including coupling the second plurality of conductive bonding portions to the first plurality of conductive bonding portions; and
forming electrical interconnections between the first element contacts of the first laminated multilayer microelectronic element and the second element contacts of the second laminated multilayer microelectronic element with the first and second pluralities of conductive bonding portions.
2. The method of claim 1 , further comprising forming a first conductive sealing portion surrounding the first plurality of conductive bonding portions at the first face of the first laminated multilayer microelectronic element and forming a second conductive sealing portion surrounding the second plurality of conductive bonding portions at the second face of the second laminated multilayer microelectronic element and mechanically and electrically bonding the second conductive sealing portion to the first conductive sealing portion.
3. The method of claim 1 , further comprising forming one or more terminal connections at a third face of the first laminated multilayer microelectronic element and forming one or more interconnections at a fourth face of the second laminated multilayer microelectronic element, the one or more terminal connections having electrical connectivity to the one or more interconnections due to the first and second patterned bonding layers.
4. The method of claim 1 , further comprising staggering a placement of conductive material for the first plurality of conductive bonding portions and the second plurality of conductive bonding portions to improve a warpage tolerance of the first and second patterned bonding layers.
5. The method of claim 1 , further comprising mechanically and electrically bonding the second patterned bonding layer to the first patterned bonding layer by thermally compressing the second laminated multilayer microelectronic element to the first laminated multilayer microelectronic element to form a bonded laminate substrate.
6. The method of claim 5 , further comprising subjecting the bonded laminate substrate to an additional bonding process, including a heated reflow process or a variable pressure oven process.
7. The method of claim 1 , further comprising forming the first laminated multilayer microelectronic element and the second laminated multilayer microelectronic element, each including:
forming one or more vias through a rigid core having a first surface and a second surface, the one or more vias adapted to carry an electrical signal between the first and second surfaces;
forming one or more first conductive routing layers, each first conductive routing layer separated by an insulating layer, at the first surface of the rigid core;
forming one or more second conductive routing layers, each second conductive routing layer separated by an insulating layer, at the second surface of the rigid core; and
electrically coupling the one or more first and second conductive routing layers to the one or more vias.
8. The method of claim 7 , further comprising controlling a warpage of the microelectronic assembly by selecting a quantity of the first and second conductive routing layers of the first laminated multilayer microelectronic element and selecting a quantity of the first and second conductive routing layers of the second laminated multilayer microelectronic element.
9. The method of claim 8 , further comprising controlling the warpage of the microelectronic assembly by determining a quantity of first and second conductive routing layers of the first laminated multilayer microelectronic element and determining a quantity of first and second conductive routing layers of the second laminated multilayer microelectronic element based on a coefficient of thermal expansion (CTE) of conductive materials of the first and second conductive routing layers of the first laminated multilayer microelectronic element and the first and second conductive routing layers of the second laminated multilayer microelectronic element and a CTE of insulating materials of the insulating layers separating the first and second conductive routing layers of the first laminated multilayer microelectronic element and of the insulating layers separating the first and second conductive routing layers of the second laminated multilayer microelectronic element.
10. The method of claim 8 , further comprising controlling the warpage of the microelectronic assembly by selecting conductive materials for the first and second conductive routing layers of the first laminated multilayer microelectronic element and the first and second conductive routing layers of the second laminated multilayer microelectronic element, and selecting insulating materials for the insulating layers separating the first and second conductive routing layers of the first laminated multilayer microelectronic element and the insulating layers separating the first and second conductive routing layers of the second laminated multilayer microelectronic element, based on a coefficient of thermal expansion (CTE) of the conductive materials and the insulating materials.