Method of making a microelectronic interconnect element with decreased conductor spacing
View Patent ↗A microelectronic interconnect element can include a plurality of first metal lines and a plurality of second metal lines interleaved with the first metal lines. Each of the first and second metal lines has a surface extending within the same reference plane. The first metal lines have surfaces above the reference plane and remote therefrom and the second metal lines have surfaces below the reference plane and remote therefrom. A dielectric layer can separate a metal line of the first metal lines from an adjacent metal line of the second metal lines.
1. A method of forming a microelectronic interconnect element, comprising:
(a) given a layered element including first and second exposed metal layers and an etch barrier layer sandwiched between the first and second metal layers, defining first metal lines by a process including etching the first exposed metal layer;
(b) forming a dielectric layer overlying the first metal lines; and
(c) defining second metal lines by a process including etching the second exposed metal layer, wherein the etch barrier layer is conductive and the method further includes removing a portion of the etch barrier layer between the first metal lines prior to step (b) and removing a portion of the etch barrier layer between the second metal lines after step (c).
2. The method of forming the microelectronic interconnect element as claimed in claim 1 , wherein a pitch between a metal line of the first metal lines and an adjacent metal line of the second metal lines is smaller than a first pitch between the first metal lines obtained by etching the first exposed metal layer and is smaller than a second pitch between the second metal lines obtained by etching the second exposed metal layer.
3. The method of forming the microelectronic interconnect element as claimed in claim 2 , wherein the first pitch is equal to at least twice a width of one of the first metal lines, and second pitch is equal to at least twice a width of one of the second metal lines, such that, in a direction of the widths of the first metal lines, at least some of the first metal lines are insulated and spaced from at least some of the second metal lines by less than the width of one of the first metal lines.
4. The method of forming the microelectronic interconnect element as claimed in claim 3 , wherein the at least some of the first metal lines are insulated and spaced from the at least some of the second metal lines by less than 10% of the width of one of the first metal lines.
5. The method of forming the microelectronic interconnect element as claimed in claim 3 , wherein the widths of the first and second metal lines are less than about 60 microns.
6. The method of forming the microelectronic interconnect element as claimed in claim 3 , wherein the widths of the first and second metal lines are at most about 20 microns.
7. The method of forming the microelectronic interconnect element as claimed in claim 3 , wherein the widths of the first and second metal lines are uniform and are at most about 10 microns.
8. The method of forming the microelectronic interconnect element as claimed in claim 1 , wherein each of the first metal lines has edges extending between upper and lower surfaces of such first metal line and a width between the edges, and each of the second metal lines has edges extending between upper and lower surfaces of such second metal line and a width between the edges, and a spacing between the edge of one of the first metal lines and an adjacent edge of one of the second metal lines is smaller than the widths of the adjacent first and second metal lines.
9. The method of forming the microelectronic interconnect element as claimed in claim 1 , wherein the dielectric layer is formed by pressing a dielectric material onto the first metal lines, such that portions of the dielectric layer separate the first metal lines from one another.