Preferred state encoding in non-volatile memories
The invention pertains to non-volatile memory devices, and more particularly to advantageously encoding data in non-volatile devices in a flexible manner by both NVM manufacturers and NVM users. Multiple methods of preferred state encoding (PSE) and/or error correction code (ECC) encoding may be used in different pages or blocks in the same NVM device for different purposes which may be dependent on the nature of the data to be stored.
1. An electronic system, comprising:
a processor;
a main memory coupled to the processor;
a memory interface coupled to the processor and the main memory;
a memory controller coupled to the memory interface; and
a first non-volatile memory (NVM) integrated circuit coupled to the memory controller, the NVM integrated circuit further comprising:
a memory array having a plurality of pages, a page buffer coupled to the memory array, and a data input/output interface coupled to the page buffer,
wherein:
a first page in the memory array is selected for programming,
first user write data is stored in the page buffer,
preferred state encoding (PSE) is applied to the first user data to generate first PSE encoded write data which is stored in the page buffer according to a first allocation map,
error correction code (ECC) encoding is applied to the first PSE encoded write data to generate first ECC encoded write data which is stored in the page buffer according to the first allocation map, and
the contents of the page buffer are programmed into the selected first page in the memory array.
2. The electronic system of claim 1 , wherein the first allocation map is stored in one of the group consisting of: the processor, the main memory, the memory interface, the memory controller, and the NVM integrated circuit.
3. The electronic system of claim 1 , further comprising:
a second NVM integrated circuit coupled to the memory controller, wherein the first allocation map is stored in the second NVM integrated circuit.
4. The electronic system of claim 1 , further comprising:
a network interface card (NIC) wherein:
the NIC is coupled to the processor, the main memory, and the memory interface internal to the electronic system,
the NIC is coupled to an external system, and
the second allocation map is stored in the external system.
5. The electronic system of claim 4 , wherein the first user write data is transferred from one of the group consisting of: the main memory, the first NVM integrated circuit, and the external system.
6. The electronic system of claim 3 , wherein the first user write data is transferred from one of the group consisting of: the main memory, the first NVM integrated circuit, and the second NVM integrated circuit.
7. The electronic system of claim 2 , wherein the first user write data is transferred from one of the group consisting of: the main memory and the first NVM integrated circuit.
8. The electronic system of claim 1 , wherein the first user write data is transferred from one of the group consisting of: the main memory and the first NVM integrated circuit.
9. The electronic system of claim 1 , wherein:
a second page in the memory array is selected for programming,
second user write data is stored in the page buffer,
preferred state encoding (PSE) is applied to the second user data to generate first PSE encoded write data which is stored in the page buffer according to a second allocation map different from the first allocation map,
error correction code (ECC) encoding is applied to the second PSE encoded write data to generate second ECC encoded write data which is stored in the page buffer according to the first allocation map, and
the contents of the page buffer are programmed into the selected second page in the memory array.
10. The electronic system of claim 9 , wherein:
the first allocation map is stored in one of the group consisting of: the processor, the main memory, the memory interface, the memory controller, and the first NVM integrated circuit, and
the second allocation map is stored in one of the group consisting of: the processor, the main memory, the memory interface, the memory controller, and the first NVM integrated circuit.
11. The electronic system of claim 9 , further comprising:
a second NVM integrated circuit wherein:
the first allocation map is stored in one of the group consisting of: the processor, the main memory, the memory interface, the memory controller, the first NVM integrated circuit, and the second NVM integrated circuit, and
the second allocation map is stored in one of the group consisting of: the processor, the main memory, the memory interface, the memory controller, and the first NVM integrated circuit, and the second NVM integrated circuit.
12. The electronic system of claim 9 , further comprising:
a network interface card (NIC) wherein:
the NIC is coupled to the processor, the main memory, and the memory interface internal to the electronic system,
the NIC is coupled to an external system, and
the first allocation map is stored in the external system.
13. The electronic system of claim 9 , further comprising:
a network interface card (NIC) wherein:
the NIC is coupled to the processor, the main memory, and the memory interface internal to the electronic system,
the NIC is coupled to an external system, and
the second allocation map is stored in the external system.
14. A non-volatile memory (NVM) device, comprising:
a memory array;
a first page buffer coupled to the memory array;
a data input/output (I/O) interface coupled to the first page buffer;
a first error correction code (ECC) circuit coupled to the first page buffer to generate first ECC encoded write data which is stored in the first page buffer; and
a first preferred state encoding (PSE) circuit coupled to the first page buffer to generate first PSE encoded write data which is stored in the first page buffer.
15. The NVM device of claim 14 , further comprising:
a second page buffer coupled to the memory array and the data I/O interface.
16. The NVM device of claim 15 , wherein:
the memory array further comprises a first memory plane and a second memory plane,
the first memory plane is coupled to the first page buffer, and
the second memory plane is coupled to the second page buffer.
17. The NVM device of claim 16 , further comprising:
a second error correction code (ECC) circuit coupled to the second page buffer; and
a second preferred state encoding (PSE) circuit coupled to the second page buffer.
18. The NVM device of claim 15 , further comprising:
a second error correction code (ECC) circuit coupled to the second page buffer; and
a second preferred state encoding (PSE) circuit coupled to the second page buffer.
19. The NVM device of claim 15 , further comprising:
a multiplexer circuit coupled to the data I/O interface, the first page buffer, and the second page buffer.
20. The NVM device of claim 19 , further comprising:
a second error correction code (ECC) circuit coupled to the second page buffer; and
a second preferred state encoding (PSE) circuit coupled to the second page buffer.