IP Library Granted Patent US 9,871,019
Granted Patent B2
US 9,871,019 · App. 15/209,034 · Granted Jan 16, 2018

Flipped die stack assemblies with leadframe interconnects

Inventors: Ashok S. Prabhu (San Jose, CA); Rajesh Katkar (San Jose, CA); Liang Wang (Milpitas, CA); Cyprian Emeka Uzoh (San Jose, CA)
Assignee: Invensas Corporation
H01L25/0657H01L23/3157H01L23/49541H01L24/96H01L2224/04105H01L2224/18
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Quick Facts
Patent No.
US 9,871,019
App. No.
15/209,034
Granted
Jan 16, 2018
Kind
B2
Abstract

A microelectronic assembly includes a stack of microelectronic elements, e.g., semiconductor chips, each having a front surface defining a respective plane of a plurality of planes. A leadframe interconnect joined to a contact at a front surface of each chip may extend to a position beyond the edge surface of the respective microelectronic element. The chip stack is mounted to support element at an angle such that edge surfaces of the chips face a major surface of the support element that defines a second plane that is transverse to, i.e., not parallel to the plurality of parallel planes. The leadframe interconnects are electrically coupled at ends thereof to corresponding contacts at a surface of the support element.

Claims (19)

1. A microelectronic assembly, comprising:

a chip stack comprising a plurality of microelectronic elements having front surfaces, each front surface defining a respective plane of a plurality of planes, each microelectronic element having a plurality of contacts at the front surface and an edge surface extending away from its front surface, and a dielectric region on an edge surface of the respective microelectronic element, the dielectric region having a remote surface displaced in a lateral direction beyond the edge surface of the respective microelectronic element;

a plurality of leadframe interconnects each electrically coupled to a contact on one of the microelectronic elements and each having an end at the remote surface of the dielectric region of the respective microelectronic element;

a support element having a plurality of electrically conductive contacts insulated from one another at a major surface thereof, the major surface defining a second plane non-parallel to the plurality of parallel planes, wherein the chip stack is mounted to the support element with the remote surfaces of the dielectric regions towards the major surface and the leadframe interconnects facing and joined with corresponding contacts at the major surface.

2. The microelectronic assembly as claimed in claim 1 , wherein a plurality of the chip stacks are mounted to the support element at a separation of at least 100 microns between first and second adjacent chip stacks.

3. The microelectronic assembly as claimed in claim 1 , wherein the leadframe is a molded leadframe.

4. The microelectronic assembly as claimed in claim 1 , wherein the ends of the leadframe interconnects coupled to the respective microelectronic element extend beyond the remote surface of the dielectric region on the edge surface of the respective microelectronic element.

5. The microelectronic assembly as claimed in claim 1 , wherein the ends of the leadframe interconnects coupled to the respective microelectronic element are flush with or recessed relative to the remote surface of the dielectric region on the edge surface of the respective microelectronic element.

6. The microelectronic assembly as claimed in claim 5 , wherein the ends of the leadframe interconnects coupled to the respective microelectronic element are disposed between the dielectric region extending from the respective microelectronic element and the dielectric region extending from the microelectronic element adjacent to the respective microelectronic element.

7. The microelectronic assembly as claimed in claim 1 , wherein the leadframe interconnects are metallurgically joined with the contacts on the respective microelectronic element through electrically conductive bumps consisting essentially of gold, nickel, tin or copper.

8. The microelectronic assembly as claimed in claim 1 , further comprising metal superstructures deposited by a process including plating onto the contacts, each superstructure comprising a layer consisting essentially of copper and projecting at least 5 microns above the surface of the support element, wherein the leadframe interconnects are metallurgically joined directly to the metal superstructures, or are joined to the metal superstructures with an electrically conductive bond material.

9. The microelectronic assembly as claimed in claim 8 , wherein the metal superstructures have areas defined by areas of major surfaces of the contacts.

10. A microelectronic assembly, comprising:

a chip stack comprising a plurality of microelectronic elements having front surfaces, each front surface defining a respective plane of a plurality of planes, each microelectronic element having a plurality of contacts at the front surface and an edge surface extending away from its front surface in a first direction transverse to its front surface, and a dielectric region overlying an edge surface of the respective microelectronic element, the dielectric region extending from the edge surface in a second direction transverse to the edge surface to a remote surface displaced in the second direction beyond the edge surface of the respective microelectronic element;

a plurality of leadframe interconnects each electrically coupled to a contact on one of the microelectronic elements and each having an end at the remote surface of the dielectric region of the respective microelectronic element;

a support element having a plurality of electrically conductive contacts insulated from one another at a major surface thereof, the major surface defining a second plane non-parallel to the plurality of parallel planes, wherein the chip stack is mounted to the support element with the remote surfaces of the dielectric regions towards the major surface and the leadframe interconnects facing and joined with corresponding contacts at the major surface.

11. The microelectronic assembly as claimed in claim 10 , wherein the remote surface of the dielectric region of each of the microelectronic elements is closer to the major surface of the support element than the edge surface of the respective microelectronic element.

12. The microelectronic assembly as claimed in claim 10 , further comprising a reinforcing underfill material surrounding individual connections between the leadframe interconnects and the contacts of the support element.

13. The microelectronic assembly as claimed in claim 12 , wherein each of the dielectric regions extends at least partially into the reinforcing underfill material in the second direction.

Assignments (4)
CHANGE OF NAME Recorded Nov 24, 2025
From: INVENSAS CORPORATION
To: INVENSAS LLC
Reel/Frame 073508/0758 →
CHANGE OF NAME Recorded Nov 24, 2025
From: INVENSAS LLC
To: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
Reel/Frame 073508/0807 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2016
From: PRABHU, ASHOK S.; KATKAR, RAJESH; WANG, LIANG; UZOH, CYPRIAN EMEKA
To: INVENSAS CORPORATION
Reel/Frame 039157/0792 →
Continuity (3)
Provisional Application 62219015 · Sep 15, 2015
Provisional Application 62194051 · Jul 17, 2015
Related Publication 20170018485A1 · Jan 19, 2017