IP Library Granted Patent US 10,622,291
Granted Patent B2
US 10,622,291 · App. 15/710,110 · Granted Apr 14, 2020

SSI PoP

Inventor: Belgacem Haba (Saratoga, CA)
Assignee: Invensas Corporation
H01L23/498H01L21/486H01L21/4846H01L21/4853H01L21/56H01L21/563H01L21/6835H01L21/78H01L23/04H01L23/3121H01L23/3135H01L23/3142H01L23/3675H01L23/49811H01L23/49816H01L23/49822H01L23/49827H01L23/49838H01L24/17H01L24/81H01L24/97H01L25/0652H01L25/105H01L25/16H01L25/18H01L24/13H01L24/16H01L24/32H01L25/0655H01L25/50H01L2221/68345H01L2221/68359H01L2221/68381H01L2224/1134H01L2224/133H01L2224/1329H01L2224/13294H01L2224/16113H01L2224/16227H01L2224/32225H01L2224/73204H01L2224/8188H01L2224/81192H01L2224/81444H01L2224/81447H01L2224/81455H01L2224/81862H01L2224/97H01L2225/0652H01L2225/06517H01L2225/06548H01L2225/06572H01L2225/06589H01L2225/1058H01L2924/1427H01L2924/15192H01L2924/15311H01L2924/19041H01L2924/19102
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Quick Facts
Patent No.
US 10,622,291
App. No.
15/710,110
Granted
Apr 14, 2020
Kind
B2
Abstract

An assembly can include a first microelectronic package and a circuit structure comprising a plurality of dielectric layers and electrically conductive features thereon. The first package can include a substrate having a plurality of first contacts at a first or second surface thereof and a plurality of second contacts at the first surface thereof, and a first microelectronic element having a plurality of element contacts at a front surface thereof. The first contacts can be electrically coupled with the element contacts of the first microelectronic element. The electrically conductive features of the first circuit structure can include a plurality of bumps at the first surface of the circuit structure facing the second contacts of the substrate and joined thereto, a plurality of circuit structure contacts at a second surface of the circuit structure, and a plurality of traces coupling at least some of the bumps with the circuit structure contacts.

Claims (30)

1. A method of making an assembly, comprising:

forming a circuit structure mechanically coupled to a surface of a carrier, the forming including:

forming a first dielectric layer mechanically coupled to the carrier and forming a plurality of circuit structure contacts and a plurality of conductive traces supported by the first dielectric layer, at least some of the plurality of conductive traces having maximum widths less than two microns,

forming a second dielectric layer mechanically coupled with the first dielectric layer, wherein the carrier provides support during formation of the first and second dielectric layers of the circuit structure thereon, and

forming bumps at a surface of the second dielectric layer opposite from a surface of the first dielectric layer that faces the carrier, the bumps being electrically coupled with the plurality of circuit structure contacts through the plurality of conductive traces;

joining the bumps of the circuit structure with a plurality of second contacts at a first surface of a substrate having a first microelectronic element mounted to first contacts of the substrate, the second contacts facing the bumps;

providing an encapsulant extending between the circuit structure and the substrate, wherein a portion of the encapsulant extends between a second surface of the circuit structure and an edge surface of the substrate; and

separating the circuit structure from the carrier,

wherein the plurality of circuit structure contacts are configured for connection with corresponding contacts of a component external to the assembly, and

wherein the joining the bumps is performed to unite the circuit structure with the substrate, the method further comprising providing an underfill surrounding and mechanically reinforcing individual bumps of the assembly and contacting the first surface of the substrate and a surface of the circuit structure facing the substrate, the underfill being separate from the encapsulant, the underfill having a composition different from a composition of the substrate, and different from a composition of the circuit structure.

2. The method as claimed in claim 1 , wherein the component external to the assembly is a microelectronic package having a second microelectronic element therein, and the corresponding contacts of the component are terminals at a surface of the microelectronic package electrically coupled with element contacts of the second microelectronic element,

the method further comprising joining at least some of the plurality of circuit structure contacts with the terminals of the microelectronic package.

3. The method as claimed in claim 1 , wherein the component external to the assembly is a second microelectronic element, the method further comprising joining at least some of the plurality of circuit structure contacts with element contacts of the second microelectronic element.

4. The method as claimed in claim 1 , wherein the plurality of conductive traces are first traces, and the maximum widths of the first traces are defined by no first traces having greater widths than two microns, and the forming of the circuit structure includes forming second traces after forming the first traces, the second traces electrically coupled with the first traces, and at least some of the second traces having maximum widths larger than the maximum widths of the first traces.

5. The method as claimed in claim 1 , wherein the substrate is a first substrate, the method further comprising:

joining the bumps of the circuit structure with a plurality of second contacts at a first surface of a second substrate having a second microelectronic element mounted to first contacts of the second substrate, the second contacts facing the bumps; and

after separating the circuit structure from the carrier, singulating the assembly into a first assembly including the first substrate and a second assembly including the second substrate.

6. A method of making an assembly, comprising:

forming a circuit structure mechanically coupled to a surface of a carrier, the forming including:

forming a first dielectric layer mechanically coupled to the carrier and forming a plurality of circuit structure contacts and a plurality of conductive traces supported by the first dielectric layer, at least some of the plurality of conductive traces having maximum widths less than two microns,

forming a second dielectric layer mechanically coupled with the first dielectric layer, and

forming bumps at a surface of the second dielectric layer opposite from a surface of the first dielectric layer that faces the carrier, the bumps being electrically coupled with the plurality of circuit structure contacts through the plurality of conductive traces;

joining the bumps of the circuit structure with a plurality of second contacts at a first surface of a substrate having a first microelectronic element mounted to first contacts of the substrate, the second contacts facing the bumps;

providing an encapsulant extending between the circuit structure and the substrate, wherein a portion of the encapsulant extends between a second surface of the circuit structure and an edge surface of the substrate; and

separating the circuit structure from the carrier,

wherein the plurality of circuit structure contacts are configured for connection with corresponding contacts of a component external to the assembly,

further comprising connecting at least some of the circuit structure contacts with the corresponding contacts of the component external to the assembly, wherein the carrier provides support during formation of the first and second dielectric layers of the circuit structure thereon, and the circuit structure is separated from the carrier prior to the connecting,

wherein the joining the bumps is performed to unite the circuit structure with the substrate, the method further comprising providing an underfill surrounding and mechanically reinforcing individual bumps of the assembly and contacting the first surface of the substrate and a surface of the circuit structure facing the substrate, the underfill being separate from the encapsulant, the underfill having a composition different from a composition of the substrate, and different from a composition of the circuit structure.

7. The method as claimed in claim 6 , wherein a release layer maintains the circuit structure atop the carrier during formation of the first and second dielectric layers, and the circuit structure is separated from the carrier by releasing the release layer.

8. The method as claimed in claim 6 , wherein the circuit structure is separated from the carrier by abrading the carrier.

Assignments (4)
CHANGE OF NAME Recorded Nov 24, 2025
From: INVENSAS CORPORATION
To: INVENSAS LLC
Reel/Frame 073508/0758 →
CHANGE OF NAME Recorded Nov 24, 2025
From: INVENSAS LLC
To: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
Reel/Frame 073508/0807 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 21, 2017
From: HABA, BELGACEM
To: INVENSAS CORPORATION
Reel/Frame 043654/0670 →
Continuity (3)
Division 14958190 · Dec 3, 2015
Provisional Application 62159136 · May 8, 2015
Related Publication 20180068930A1 · Mar 8, 2018