Microelectronic interconnect element with decreased conductor spacing

1. A microelectronic interconnect element, comprising:

a plurality of first metal lines each having a lower surface whose width and length extend within a reference plane, an upper surface remote from the reference plane, and edges extending between the upper and lower surfaces, a first distance between the upper and lower surfaces of such first metal line defining a thickness of such first metal line;

a plurality of second metal lines interleaved with the plurality of first metal lines in a direction of the width of the plurality of first metal lines, each of the plurality of second metal lines having an upper surface whose width and length extend within the reference plane and a lower surface remote from the reference plane, a second distance between the upper and lower surfaces of such second metal line defining a thickness of such second metal line;

a dielectric layer separating a metal line of the plurality of first metal lines from an adjacent metal line of the plurality of second metal lines; and

a conductive pad extending in directions of the reference plane and a conductive via extending from the conductive pad through the dielectric layer,

wherein a pitch between the metal line of the plurality of first metal lines and the adjacent metal line of the plurality of second metal lines is smaller than a first pitch between adjacent ones of the plurality of first metal lines and is smaller than a second pitch between adjacent ones of the plurality of second metal lines, and

wherein the first pitch is equal to at least twice a width of one of the plurality of first metal lines, and the second pitch is equal to at least twice a width of one of the plurality of second metal lines, such that, in a direction of the widths of the plurality of first metal lines, edges of at least some of the plurality of first metal lines are insulated and spaced from edges of at least some of the plurality of second metal lines by much less than the width of one of the plurality of first metal lines.

2. The microelectronic interconnect element as claimed in claim 1 , wherein the conductive via includes a solid metal bump and the conductive pad includes a metal ring connected to at least one of the plurality of first metal lines and a conductive joining material within the metal ring, the solid metal bump being joined to the conductive joining material.

3. The microelectronic interconnect element as claimed in claim 2 , wherein the solid metal bump is an etched metal bump.

4. The microelectronic interconnect element as claimed in claim 2 , wherein the metal ring and the plurality of first metal lines are formed from the same metal layer.

5. The microelectronic interconnect element as claimed in claim 1 , wherein the edges of the at least some of the plurality of first metal lines are insulated and spaced from the edges of the at least some of the plurality of second metal lines by less than 10% of the width of one of the plurality of first metal lines.

6. The microelectronic interconnect element as claimed in claim 1 , wherein the plurality of first metal lines and the plurality of second metal lines are formed by etching.

7. The microelectronic interconnect element as claimed in claim 1 , wherein at least some of the plurality of first metal lines and at least some of the plurality of second metal lines are formed by plating.

8. The microelectronic interconnect element as claimed in claim 1 , wherein the widths of the plurality of first metal lines and plurality of second metal lines are less than about 60 microns.

9. The microelectronic interconnect element as claimed in claim 1 , wherein the widths of the plurality of first metal lines and plurality of second metal lines are at most about 20 microns.

10. The microelectronic interconnect element as claimed in claim 1 , wherein the widths of the plurality of first metal lines and plurality of second metal lines are uniform and are at most about 10 microns.

11. A microelectronic interconnect element, comprising:

a plurality of first metal lines each having a lower surface whose width and length extend within a reference plane, an upper surface remote from the reference plane, and edges extending between the upper and lower surfaces, a first distance between the upper and lower surfaces of such first metal line defining a thickness of such first metal line;

a plurality of second metal lines interleaved with the plurality of first metal lines in a direction of the width of the plurality of first metal lines, each of the plurality of second metal lines having an upper surface whose width and length extend within the reference plane and a lower surface remote from the reference plane, a second distance between the upper and lower surfaces of such second metal line defining a thickness of such second metal line;

a dielectric layer separating a metal line of the plurality of first metal lines from an adjacent metal line of the plurality of second metal lines; and

a conductive pad extending in directions of the reference plane and a conductive via extending from the conductive pad through the dielectric layer,

wherein each of the plurality of first metal lines has edges extending between upper and lower surfaces of such first metal line and a width between the edges, and each of the plurality of second metal lines has edges extending between upper and lower surfaces of such second metal line and a width between the edges, and a spacing between the edge of one of the plurality of first metal lines and an adjacent edge of one of the plurality of second metal lines is smaller than the widths of the adjacent ones of the pluralities of first and second metal lines.

12. The microelectronic interconnect element as claimed in claim 11 , wherein the conductive via includes a solid metal bump and the conductive pad includes a metal ring connected to at least one of the plurality of first metal lines and a conductive joining material within the metal ring, the solid metal bump being joined to the conductive joining material.

13. The microelectronic interconnect element as claimed in claim 12 , wherein the solid metal bump is an etched metal bump.

14. The microelectronic interconnect element as claimed in claim 12 , wherein the metal ring and the plurality of first metal lines are formed from the same metal layer.

15. The microelectronic interconnect element as claimed in claim 11 , wherein the edges of the at least some of the plurality of first metal lines are insulated and spaced from the edges of the at least some of the plurality of second metal lines by less than 10% of the width of one of the plurality of first metal lines.

16. The microelectronic interconnect element as claimed in claim 11 , wherein the plurality of first metal lines and the plurality of second metal lines are formed by etching.

17. The microelectronic interconnect element as claimed in claim 11 , wherein at least some of the plurality of first metal lines and at least some of the plurality of second metal lines are formed by plating.

18. The microelectronic interconnect element as claimed in claim 11 , wherein the widths of the plurality of first metal lines and plurality of second metal lines are less than about 60 microns.

19. The microelectronic interconnect element as claimed in claim 11 , wherein the widths of the plurality of first metal lines and plurality of second metal lines are at most about 20 microns.

20. The microelectronic interconnect element as claimed in claim 11 , wherein the widths of the plurality of first metal lines and plurality of second metal lines are uniform and are at most about 10microns.