Packaged microelectronic device for a package-on-package device
View Patent ↗Methods and apparatuses relate generally to a packaged microelectronic device for a package-on-package device (“PoP”) with enhanced tolerance for warping. In one such packaged microelectronic device, interconnect structures are in an outer region of the packaged microelectronic device. A microelectronic device is coupled in an inner region of the packaged microelectronic device inside the outer region. A dielectric layer surrounds at least portions of shafts of the interconnect structures and along sides of the microelectronic device. The interconnect structures have first ends thereof protruding above an upper surface of the dielectric layer a distance to increase a warpage limit for a combination of at least the packaged microelectronic device and one other packaged microelectronic device directly coupled to protrusions of the interconnect structures.
1. A method for forming a packaged microelectronic device, comprising:
forming interconnect structures in and coupled to an outer region of a redistribution layer of the packaged microelectronic device;
providing a microelectronic device in and coupled to an inner region of a redistribution layer of the packaged microelectronic device inside the outer region;
forming a dielectric layer surrounding at least portions of shafts of the interconnect structures and along sides of the microelectronic device; and
the interconnect structures having first ends thereof protruding above an upper surface of the dielectric layer a distance and having second ends thereof coupled to the redistribution layer, the first ends and the second ends corresponding thereto facing away from one another.
2. The method according to claim 1 , further comprising:
forming the redistribution layer over the second ends of the interconnect structures and over the microelectronic device, the second ends of the interconnect structures being opposite the first ends of the interconnect structures, the redistribution layer including interconnect pads in both the inner region and the outer region along a surface of the redistribution layer.
3. The method according to claim 1 , wherein the interconnect structures include plating-formed posts.
4. The method according to claim 1 , wherein the interconnect structures include wire bond wires.
5. The method according to claim 1 , further comprising forming interconnect pads located on the first ends of the interconnect structures.
6. The method according to claim 1 , wherein the packaged microelectronic device is a first packaged microelectronic device, the method further comprising coupling a second packaged microelectronic device to protrusions associated with the first ends of the interconnect structures with electrically conductive bonding masses to provide a package-on-package device.
7. The method according to claim 1 , wherein the first ends of at least some of the interconnect structures protruding above the upper surface of the dielectric layer are laterally displaced with respect to corresponding ones of the second ends of the interconnect structures.
8. A packaged microelectronic device, comprising:
interconnect structures in and coupled to an outer region of a redistribution layer of the packaged microelectronic device;
a microelectronic device provided in and coupled to an inner region of a redistribution layer of the packaged microelectronic device inside the outer region; and
a dielectric layer surrounding at least portions of shafts of the interconnect structures and along sides of the microelectronic device;
the interconnect structures having first ends thereof protruding above an upper surface of the dielectric layer a distance and having second ends thereof coupled to the redistribution layer, the first ends and the second ends corresponding thereto facing away from one another.
9. The packaged microelectronic device according to claim 8 , further comprising:
the redistribution layer coupled to the second ends of the interconnect structures and over the microelectronic device; and
the redistribution layer comprising interconnect pads in both the inner region and the outer region along a surface of the redistribution layer.
10. The packaged microelectronic device according to claim 8 , wherein the interconnect structures include plating-formed posts.
11. The packaged microelectronic device according to claim 8 , wherein the interconnect structures include wire bond wires.
12. The packaged microelectronic device according to claim 8 , further comprising interconnect pads located on the first ends of the interconnect structures.
13. The packaged microelectronic device according to claim 8 , wherein the packaged microelectronic device is a first packaged microelectronic device, and the first packaged microelectronic device further comprising a second packaged microelectronic device directly coupled to protrusions associated with the first ends of the interconnect structures with electrically conductive bonding masses to provide a package-on-package device.
14. The packaged microelectronic device according to claim 8 , wherein the first ends of at least some of the interconnect structures protruding above the upper surface of the dielectric layer are laterally displaced with respect to corresponding ones of the second ends of the interconnect structures.
15. The packaged microelectronic device according to claim 8 , further comprising a reinforcing layer with a stiffener material beneath the dielectric layer.
16. The packaged microelectronic device according to claim 8 , wherein the first ends protrude at least 100 microns beyond the dielectric layer.
17. The packaged microelectronic device according to claim 13 , wherein the first ends protrude to a length sufficient to accommodate warpage of the first packaged microelectronic device or the second packaged microelectronic device.