Patent Assignment
Reel/Frame 017564/0653
Assignment of Assignor's Interest
Recorded: 2006-05-04
Received: 2006-05-04
Pages: 6
Assignor
MEGIC CORPORATION
Executed: 2006-04-28
Assignee
MEGICA CORPORATION
NO. 47, PARK 2ND RD. SCIENCE-BASED INDUSTRIAL PARK, ROOM 301/302, HSINCHU, TWX, TAIWAN
Covered Properties
(29)
Low Fabrication Cost, High Performance, High Reliability Chip Scale Package
Application:
10/638,454 →
Electrode for Electroplating Planar Structures
Application:
10/462,251 →
High Performance System-on-Chip Discrete Components Using Post Passivation Process
Application:
10/445,560 →
Multiple Chips Bonded to Packaging Structure with Low Noise and Multiple Selectable Functions
Application:
10/437,355 →
Primary Chips Bonded to a Printed Circuit Board Supporting a Secondary Chip in a Chip-on-Chip Connection
Application:
10/371,506 →
Method of Metal Sputtering for Integrated Circuit Metal Routing
Application:
10/336,871 →
Capacitor for High Performance System-on-Chip Using Post Passivation Device
Application:
10/303,451 →
Thermal Compliant Semiconductor Chip Wiring Structure for Chip Scale Packaging
Application:
10/279,267 →
Post Passivation Interconnection Schemes on Top of the Ic Chips
Application:
10/278,106 →
A Capacitor for High Performance System-on-Chip Using Post Passivation Process Structure
Application:
10/156,590 →
High Performance System-on-Chip Using Post Passivation Process
Application:
10/156,412 →
A Resistor for High Performance System-on-Chip Using Post Passivation Process
Application:
10/156,589 →
An Apparatus to Electroless Plate a Metal Layer While Eliminating the Photo Electric Effect
Application:
10/117,888 →
Top Layers of Metal for High Performance Ic's
Application:
10/058,259 →
Thin Film Semiconductor Package Utilizing a Glass Substrate with Comosite Polymer/Metal Interconnect Layers
Application:
10/054,001 →
Post Passivation Metal Scheme for High-Performacne Integrated Circuit Devices
Application:
09/998,862 →
Post Passivation Metal Scheme for High-Performance Integrated Circuit Devices
Application:
10/004,027 →
Inductor Structure for High Performance System-on-Chip Using Post Passivation Process
Application:
09/970,005 →
Multiple Selectable Function Integrated Circuit Module
Application:
09/961,767 →
Structure of Ceramic Package with Integrated Passive Devices
Application:
09/953,610 →
Method Making a Low Fabrication Cost, High Performance, High Reliability Chip Scale Package
Application:
09/953,525 →
Structure of High Performance Combo Chip and Processing Method
Application:
09/953,544 →
Method for Making High-Performance Rf Integrated Circuits
Application:
09/945,436 →
Electrode for Electroplating Planar Structures
Application:
09/932,729 →
Methods of Ic Rerouting Option for Multiple Package System Applications
Application:
09/858,528 →
High Performance Sub-System Design and Assembly
Application:
09/849,039 →
Low Fabrication Cost, Fine Pitch and High Reliability Solder Bump
Application:
09/798,654 →
Reliable Metal Bumps on Top of I/O Pads After Removal of Test Probe Marks
Application:
09/783,384 →
Reliable Metal Bumps on Top of I/O Pads with Test Probe Marks
Application:
09/760,909 →