Patent Assignment
Reel/Frame 017846/0847
SECURITY AGREEMENT
Recorded: 2006-06-29
Received: 2006-06-29
Pages: 22
Assignor
VITESSE SEMICONDUCTOR CORPORATION
Executed: 2006-06-07
Assignee
OBSIDIAN, LLC, AS COLLATERAL AGENT
2951 28TH STREET, SUITE 1000, SANTA MONICA, CA, 90405, UNITED STATES
Covered Applications
(67)
High-speed data interface for connecting network devices
App. No. 60/780,628
→
DIFFERENTIAL OPTO-ELECTRONICS TRANSMITTER
App. No. 11/330,497
→
CROSSPOINT SWITCH WITH SWITCH MATRIX MODULE
App. No. 11/231,320
→
DIGITAL AUTOMATIC POWER CONTROL LOOP FOR CONTINUOUS AND BURST MODE APPLICATIONS
App. No. 11/221,609
→
DATA DE-SKEW METHOD AND SYSTEM
App. No. 11/218,331
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VARIABLE BANDWIDTH TRANSIMPEDANCE AMPLIFIER WITH ONE-WIRE INTERFACE
App. No. 11/060,061
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ADAPTIVE EQUALIZATION WITH GROUP DELAY
App. No. 11/029,297
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POWER AND AREA EFFICIENT ADAPTIVE EQUALIZATION
App. No. 10/872,108
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Physical coding sublayer transcoding
App. No. 10/871,164
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INTEGRATED CIRCUIT IMPLEMENTATION FOR POWER AND AREA EFFICIENT ADAPTIVE EQUALIZATION
App. No. 10/872,307
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METHOD AND APPARATUS FOR CONFIGURING THE OPERATION OF AN INTEGRATED CIRCUIT
App. No. 10/852,586
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OPTICAL DISPERSION CORRECTION IN TRANSIMPEDANCE AMPLIFIERS
App. No. 10/841,948
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METHOD AND APPARATUS FOR IMPROVED HIGH-SPEED FEC ADAPTIVE EQUALIZATION
App. No. 10/810,271
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OUTPUT CLOCK ADJUSTMENT FOR A DIGITAL I/O BETWEEN PHYSICAL LAYER DEVICE AND MEDIA ACCESS CONTROLLER
App. No. 10/754,204
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SWITCHING MODE REGULATOR FOR SFP ETHERNET ADAPTOR
App. No. 10/754,250
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METHOD FOR DETECTING LINK PARTNER STATE DURING AUTO NEGOTIATION AND SWITCHING LOCAL STATE TO ESTABLISH LINK
App. No. 10/754,256
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DATA LOOP PORT ACCELERATION CIRCUIT
App. No. 10/724,957
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METHOD OF OVERTONE SELECTION AND LEVEL CONTROL IN AN INTEGRATED CIRCUIT CMOS NEGATIVE RESISTANCE OSCILLATOR TO ACHIEVE LOW JITTER
App. No. 10/721,910
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METHOD AND APPARATUS FOR IMPROVED HIGH-SPEED ADAPTIVE EQUALIZATION
App. No. 10/677,123
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MEANS AND A METHOD FOR SWITCHING DATA PACKETS OR FRAMES
App. No. 10/617,884
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Multi-channel line interface unit with on-chip clock management
App. No. 10/462,214
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Channel status management system for multi-channel LIU
App. No. 10/462,213
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Packet forwarding method and system
App. No. 10/429,267
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GBIT/S TRANSCEIVER WITH BUILT-IN SELF TEST FEATURES
App. No. 10/428,326
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ON-CHIP CALIBRATED SOURCE TERMINATION FOR VOLTAGE MODE DRIVER AND METHOD OF CALIBRATION THEREOF
App. No. 10/411,993
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SELF-ALIGNED BIPOLAR TRANSISTOR
App. No. 10/364,075
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APPARATUS AND METHOD FOR INTER-CHIP OR CHIP-TO-SUBSTRATE CONNECTION WITH A SUB-CARRIER
App. No. 10/308,458
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Serial ATA frame structure routing circuitry and protocols
App. No. 10/306,350
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FAST LOCKING CLOCK AND DATA RECOVERY UNIT
App. No. 10/295,276
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SYSTEM AND METHOD FOR COMMUNICATING BETWEEN A NUMBER OF ELEMENTS AND A METHOD FOR CONFIGURING AND TESTING THE SYSTEM
App. No. 10/289,227
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ADJUSTMENT OF A CLOCK DUTY CYCLE
App. No. 10/282,398
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MULTIPLE CHANNEL ADAPTIVE DATA RECOVERY SYSTEM
App. No. 10/266,383
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MULTIPLE ELEMENT CONTROLLED OPTICAL COUPLING
App. No. 10/222,341
→
TRANSFORMERLESS ETHERNET CONTROLLER
App. No. 10/189,619
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DUAL-MIXER LOSS OF SIGNAL DETECTION CIRCUIT
App. No. 10/159,648
→
CONTROL TECHNIQUES AND DEVICES FOR AN OPTICAL SWITCH ARRAY
App. No. 10/150,531
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PRECISE PHASE DETECTOR
App. No. 10/145,412
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A SYSTEM AND A METHOD FOR MAINTAINING QUALITY OF SERVICE THROUGH A CONGESTED NETWORK
App. No. 10/139,338
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DATA SWITCHING SYSTEM
App. No. 10/138,496
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CLOCK AND DATA RECOVERY WITH A FEEDBACK LOOP TO ADJUST THE SLICE LEVEL OF AN INPUT SAMPLING CIRCUIT
App. No. 10/119,545
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HIGH BANDWIDTH CLOCK BUFFER
App. No. 10/099,668
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METHOD OF CONTROLLING THE TURN OFF CHARACTERISTICS OF A VCSEL DIODE
App. No. 10/096,739
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TIME BASED PACKET SCHEDULING AND SORTING SYSTEM
App. No. 10/096,442
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METHOD AND APPARATUS FOR SCHEDULING DATA ON A MEDIUM
App. No. 10/081,152
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HIGH SPEED CROSS POINT SWITCH ROUTING CIRCUIT WITH WORD-SYNCHRONOUS SERIAL BACK PLANE
App. No. 10/074,106
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RZ RECOVERY
App. No. 10/066,982
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HIGH SPEED CROSS POINT SWITCH ROUTING CIRCUIT WITH WORD-SYNCHRONOUS SERIAL BACK PLANE
App. No. 10/047,166
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SCALABLE CLOCK DISTRIBUTION FOR MULTIPLE CRU ON THE SAME CHIP
App. No. 10/041,888
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VERSATILE OPTICAL SWITCHING FOR WAVELENGTH-DIVISION MULTIPLEXED SYSTEM
App. No. 09/683,360
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AUTOMATIC LOAD BALANCING IN SWITCH FABRICS
App. No. 10/020,491
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LOW TEMPERATURE ALUMINUM PLANARIZATION PROCESS
App. No. 09/992,743
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OPTICAL ROUTERS AND REDUNDANCY
App. No. 10/012,207
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LOW-DENSITY PARITY CHECK FORWARD ERROR CORRECTION
App. No. 10/044,413
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MONOLITHIC LOSS-OF-SIGNAL DETECT CIRCUITRY
App. No. 09/976,511
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PRECISION ON-CHIP TRANSMISSION LINE TERMINATION
App. No. 09/974,451
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ACTUATOR-CONTROLLED MIRROR WITH Z-STOP MECHANISM
App. No. 09/956,609
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PROGRAMMABLE ANALOG TAPPED DELAY LINE FILTER HAVING CASCADED DIFFERENTIAL DELAY CELLS
App. No. 09/955,563
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METHOD AND APPARATUS FOR IMPROVED HIGH-SPEED ADAPTIVE EQUALIZATION
App. No. 09/955,278
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OUTPUT DRIVER FOR HIGH SPEED ETHERNET TRANSCEIVER
App. No. 09/894,388
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LIMITING AMPLIFIER MODULATOR DRIVER
App. No. 09/892,807
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TRANSPARENT TRANSPORT OVERHEAD MAPPING
App. No. 09/882,582
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CROSSPOINT SWITCH WITH SWITCH MATRIX MODULE
App. No. 09/878,054
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PRODUCT CODE BASED FORWARD ERROR CORRECTION SYSTEM
App. No. 09/874,158
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REDUCED GMII WITH INTERNAL TIMING COMPENSATION
App. No. 09/870,394
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CLOCK BUFFER WITH DC OFFSET SUPPRESSION
App. No. 09/865,008
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PAD CALIBRATION CIRCUIT WITH ON-CHIP RESISTOR
App. No. 09/850,530
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APPARATUS AND METHOD FOR ANGLED COAXIAL TO PLANAR STRUCTURE BROADBAND TRANSITION
App. No. 09/837,615
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