IP Library Assignment 018006/0855
Patent Assignment
Reel/Frame 018006/0855

Assignment of Assignor's Interest

Recorded: 2006-06-20 Pages: 4
Assignors
ONG, ADRIAN E.
Executed: 2006-06-19
BALIGA, NARESH
Executed: 2006-06-19
LIN, CHIATE
Executed: 2006-06-19
Assignee
INAPAC TECHNOLOGY, INC.
2290 NORTH FIRST STREET, SUITE 201, SAN JOSE, CALIFORNIA, 95131
Covered Property (1)
Shared Memory Bus Architecture for System with Processor and Memory Units
Patent: 7,466,160 →
Application: 11/472,016 →
Publication: US 2007/0013402
Related Assignments (3)
Other recorded transfers of the patent in this record — the chain of ownership.
Ucc Financing Statement Filed in California Aug 15, 2008
From: INAPAC TECHNOLOGY, INC.
To: CARR & FERRELL LLP
Reel/Frame 021425/0952 →
Release of Security Agreement (Ca) Jan 22, 2009
From: CARR & FERRELL LLP
To: INAPAC TECHNOLOGY, INC.
Reel/Frame 022158/0338 →
Assignment of Assignor's Interest Apr 28, 2009
From: INAPAC TECHNOLOGY, INC.
To: RAMBUS INC.
Reel/Frame 022597/0896 →