Patent Assignment
Reel/Frame 018113/0725
Assignment of Assignor's Interest
Recorded: 2006-07-19
Pages: 3
Assignor
NAGAI, TAKESHI
Executed: 2006-06-21
Assignee
KABUSHIKI KAISHA TOSHIBA
1-1, SHIBAURA 1-CHOME, MINATO-KU, TOKYO 105-8001, JAPAN
Covered Property
(1)
Semiconductor Memory in Which Error Correction Is Performed by on-Chip Error Correction Circuit