IP Library › Assignment 018653/0362
Patent Assignment
Reel/Frame 018653/0362

Assignment of Assignor's Interest

Recorded: 2006-12-19 Pages: 2
Assignor
WONG, TAK KWONG
Executed: 2006-12-18
Assignee
INTEGRATED DEVICE TECHNOLOGY, INC.
6024 SILVER CREEK VALLEY ROAD, SAN JOSE, CALIFORNIA, 95138
Covered Property (1)
Using a Delay Clock to Optimize the Timing Margin of Sequential Logic
Patent: 7,647,535 →
Application: 11/612,740 →
Publication: US 2008/0143383
Related Assignments (2)
Other recorded transfers of the patent in this record — the chain of ownership.
Security Agreement Apr 5, 2017
From: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; MAGNUM SEMICONDUCTOR, INC.; ENDWAVE CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 042166/0431 →
Release of Security Interest Mar 29, 2019
From: JPMORGAN CHASE BANK, N.A.
To: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; CHIPX, INCORPORATED; ENDWAVE CORPORATION
Reel/Frame 048746/0001 →