Patent Assignment
Reel/Frame 048746/0001
Release of Security Interest
Recorded: 2019-03-29
Pages: 69
Assignor
JPMORGAN CHASE BANK, N.A.
Executed: 2019-03-29
Assignees
INTEGRATED DEVICE TECHNOLOGY, INC.
6024 SILVER CREEK VALLEY ROAD, SAN JOSE, CALIFORNIA, 95138
GIGPEAK, INC.
130 BAYTECH DRIVE, SAN JOSE, CALIFORNIA, 95134
CHIPX, INCORPORATED
130 BAYTECH DRIVE, SAN JOSE, CALIFORNIA, 95134
ENDWAVE CORPORATION
130 BAYTECH DRIVE, SAN JOSE, CALIFORNIA, 95134
MAGNUM SEMICONDUCTOR, INC.
130 BAYTECH DRIVE, SAN JOSE, CALIFORNIA, 95134
Covered Properties
(781)
System and Method for Wireless Power Transfer Using a Power Converter with a Bypass Mode
PCT:
PCT/US2016/059177 ↗
Integrated Circuits That Include a Barrier Layer Reducing Hydrogen Diffusion into a Polysillicon Resistor
Patent:
5,825,068 →
Application:
08/820,664 →
Semiconductor Package with Internal Heatsink and Assembly Method
Patent:
5,986,885 →
Application:
08/835,264 →
Local Interconnect Structure and Process for Six-Transistor Sram Cell
Patent:
5,831,899 →
Application:
08/841,985 →
Method of Detecting Metal Contaminants in a Wet Chemical Using Enhanced Semiconductor Growth Phenomena
Patent:
5,913,103 →
Application:
08/855,515 →
Method for Fair Dynamic Scheduling of Available Bandwidth Rate (Abr) Service Under Asynchronous Transfer Mode (Atm)
Patent:
5,987,031 →
Application:
08/862,125 →
Transmission Rate Calculation Scheme Using Table- Lookup
Patent:
6,137,779 →
Application:
08/862,152 →
Dual Site Loadboard Tester
Patent:
5,968,193 →
Application:
08/864,524 →
Electrically Programmable Interlevel Fusible Link for Integrated Circuits
Patent:
5,949,127 →
Application:
08/870,333 →
Method of Manufacturing a Bicmos Integrated Circuit Fully Integrated Within a Cmos Process Flow
Patent:
5,888,861 →
Application:
08/870,474 →
Mosfet with Raised Source and Drain Regions
Patent:
6,063,676 →
Application:
08/871,139 →
Apparatus for Determining Warp in Semiconductor Wafer Cassettes
Patent:
5,798,532 →
Application:
08/871,543 →
High Density Mosfet with Raised Source and Drain Regions
Patent:
6,043,129 →
Application:
08/876,540 →
Sram Cell Using Thin Gate Oxide Pulldown Transistors
Patent:
5,939,762 →
Application:
08/883,367 →
Methods and Apparatus for Error Correction
Patent:
5,887,005 →
Application:
08/883,532 →
Methods and Apparatus for Error Correction
Patent:
5,887,006 →
Application:
08/883,533 →
Methods and Apparatus for Error Correction
Patent:
5,889,793 →
Application:
08/884,151 →
Multiple Stage and Low-Complexity Motion Estimation for Interframe Video Coding
Patent:
6,011,870 →
Application:
08/896,618 →
A Method for Determining a Thermal Parameter of a Device by Measuring Thermal Resistance of a Substrate Carrying the Device
Patent:
5,997,174 →
Application:
08/897,859 →
Isolation Trenches with Protected Corners
Patent:
5,981,356 →
Application:
08/901,574 →
Miniature Active Conversion Between Microstrip and Coplanar Wave Guide
Patent:
35,869 →
Application:
08/903,239 →
Method for Testing Data Retention in a Static Random Access Memory Using Isolated Vcc Supply
Patent:
5,910,922 →
Application:
08/906,448 →
Single-Pass Variable Bit-Rate Control for Digital Video Coding
Patent:
6,192,075 →
Application:
08/918,682 →
Method for Equalization of a Quadrature Amplitude Modulated Siganl
Patent:
6,067,319 →
Application:
08/922,878 →
Extended Range Current Controlled Oscillator
Patent:
5,831,486 →
Application:
08/923,263 →
Method and Apparatus for Memory Prefetch Operation of Volatile Non-Coherent Data
Patent:
6,128,703 →
Application:
08/924,113 →
Output Driver Circuit for High Speed Digital Signal Transmission
Patent:
6,130,563 →
Application:
08/926,822 →
Testing Method and Apparatus for Identifying Disturbed Cells Within a Memory Cell Array
Patent:
6,216,239 →
Application:
08/931,201 →
Transition Between Circuit Transmission Line and Microwave Waveguide `
Patent:
6,002,305 →
Application:
08/937,754 →
Package Including Self-Aligned Laser Diode and Method of Aligning a Laser Diode
Patent:
5,870,517 →
Application:
08/946,332 →
Leadframe with Power and Ground Planes
Patent:
36,907 →
Application:
08/947,843 →
Variable-Size Spatial and Temporal Video Scaler
Patent:
6,108,047 →
Application:
08/959,314 →
Method of Forming Air Gaps for Reducing Interconnect Capacitance
Patent:
6,136,687 →
Application:
08/978,967 →
Multiple Loop Radio Frequency Synthesizer and Fm Modulator
Patent:
6,115,586 →
Application:
08/993,488 →
Method for Forming Isolation Regions Subsequent to Gate Formation and Structure Thereof
Patent:
6,069,054 →
Application:
08/997,604 →
Method and Structure for a Surface Mountable Rigid- Flex Printed Circuit Board
Patent:
5,956,234 →
Application:
09/009,650 →
Method for Fabricating Air Gap with Borderless Contact
Patent:
6,025,260 →
Application:
09/019,491 →
Sectorized Multi-Function Communication System
Patent:
6,052,582 →
Application:
09/019,821 →
Separate Byte Control on Fully Synchronous Pipelined Sram
Patent:
6,115,320 →
Application:
09/028,206 →
Circuit for Compensating for Variations in Both Temperature and Supply Voltage
Patent:
5,994,945 →
Application:
09/040,329 →
An Integrated Circuit Package Using a Gas to Insulate Electrical Conductors
Patent:
6,111,199 →
Application:
09/057,015 →
Methods of Testing Integrated Circuits to Include Data Traversal Path Identification Informaton and Related Status Information in Test Data Streams
Patent:
6,173,425 →
Application:
09/060,478 →
Multiple Stage Self-Biasing Rf Transistor Circuit
Patent:
6,064,253 →
Application:
09/063,425 →
Synchronous Sense Amplifier with Temperature and Voltage Compensated Translator
Patent:
6,037,807 →
Application:
09/080,710 →
Buffer Memory Arrays Having Nonlinear Columns for Providing Parallel Data Access Capability and Methods of Operating Same
Patent:
5,982,700 →
Application:
09/082,853 →
Highly Integrated Tri-Port Memory Buffers Having Fast Fall-Through Capability and Methods of Operating Same
Patent:
5,999,478 →
Application:
09/082,855 →
Integrated Circuit Memory Devices Having Partitioned Multi-Port Memory Arrays Therein for Increasing Data Bandwidth and Methods of Operating Same
Patent:
5,978,307 →
Application:
09/082,856 →
Methods of Controlling Memory Buffers Having Tri-Port Cache Arrays Therein
Patent:
6,216,205 →
Application:
09/082,893 →
Clock Recovery for Multiple Frequency Input Data
Patent:
6,236,697 →
Application:
09/085,841 →
High Speed Buffer Circuit with Improved Noise Immunity
Patent:
6,307,399 →
Application:
09/089,309 →
Methods and Apparatus for Generating Multiplicative Inverse Product
Patent:
6,157,939 →
Application:
09/090,798 →
Postprocessing System for Removing Blocking Artifacts in Block-Based Codecs
Patent:
6,320,905 →
Application:
09/111,827 →
Lsi Architecture and Implementation of Mpeg Video Codec
Patent:
6,584,156 →
Application:
09/118,669 →
Process for Making Six-Transistor Sram Cell Local Interconnect Structure
Patent:
6,100,128 →
Application:
09/129,254 →
Slotline-To Slotline Mounted Flip Chip
Patent:
6,094,114 →
Application:
09/136,431 →
Esd Damage Protection Using a Clamp Circuit
Patent:
6,069,782 →
Application:
09/140,619 →
Signal Transfer Devices Having Self-Timed Booster Circuits Therein
Patent:
6,114,840 →
Application:
09/154,995 →
Packet Classification State Machine
Patent:
6,167,047 →
Application:
09/157,144 →
Charge Pump for Improving Memory Cell Low Vcc Performance Without Increasing Gate Oxide Thickness
Patent:
6,215,708 →
Application:
09/164,450 →
A Method for Forming a Salicided Mosfet Structure with Tunable Oxynitride Spacer
Patent:
6,806,154 →
Application:
09/169,303 →
Apparatus and Method for Providing a Common System Interface for Processors
Patent:
6,226,756 →
Application:
09/185,126 →
Integrated Circuit Output Buffers Having Low Propagation Delay and Improved Noise Characteristics
Patent:
6,091,260 →
Application:
09/191,141 →
Differential Sense Amplifier Circuit
Patent:
6,154,064 →
Application:
09/223,265 →
Asynchronous Fifo Increment and Decrement Control for Interfaces That Operate at Differing Clock Frequencies
Patent:
6,614,798 →
Application:
09/281,520 →
Quad Data Rate Ram
Patent:
6,381,684 →
Application:
09/300,758 →
Method of Initializing an Oscillator Circuit
Patent:
6,188,290 →
Application:
09/303,578 →
Method for Forming Gate Oxides of Different Thicknesses
Patent:
6,165,918 →
Application:
09/306,654 →
Seperate Byte Control on Fully Synchronous Pipelined Sram
Patent:
6,081,478 →
Application:
09/320,410 →
Double Data Rate Synchronous Sram with 100% Bus Utilization
Integrated Circuit Output Buffers Having Feedback Switches Therein for Reducing Simultaneous Switching Noise and Improving Impedance Matching Characteristics
Patent:
6,242,942 →
Application:
09/374,630 →
Process for Preventing the Formation of Ring Defects
Patent:
6,306,771 →
Application:
09/384,752 →
Identical Gate Conductivity Type Static Random Access Memory Cell
Patent:
6,191,460 →
Application:
09/390,454 →
Reduction of Topside Movement During Temperature Cycles
Patent:
6,204,557 →
Application:
09/394,667 →
Acoustic Device Packaged at Wafer Level
Patent:
6,287,894 →
Application:
09/411,316 →
Air Gap with Borderless Contact
Patent:
6,232,647 →
Application:
09/434,544 →
Alternate Set of Registers to Service Critical Interrupts and Operating System Traps
Patent:
7,133,951 →
Application:
09/515,358 →
High frequency switch-mode DC powered computer system
Patent:
6,307,757 →
Application:
09/534,641 →
System for Controlling the Delivery of Power to Dc Computer Components
Patent:
6,694,438 →
Application:
09/584,412 →
Multiple Power Converter System Using Combining Transformers
Patent:
6,545,450 →
Application:
09/641,584 →
Multi-Step Tungsten Etchback Process to Preserve Barrier Integrity in an Integrated Circuit Structure
Patent:
6,872,668 →
Application:
09/671,667 →
Method of Forming a Photoresist Pattern Using Wasoom
Patent:
6,486,058 →
Application:
09/679,265 →
Disparity and transition density control system and method
Patent:
6,304,196 →
Application:
09/692,602 →
Method and Apparatus for Recording Real-Time Audio/Video Information Onto Recordable Compact Disc Drives
Patent:
6,950,605 →
Application:
09/738,135 →
Programmable Oscillator Circuit and Method
Conformal Surface Silicide Strap on Spacer and Method of Making Same
Noise Reduction System and Method for Reducing Switching Noise in an Interface to a Large Width Bus
Esd Protection Circuit
Dielectric Anti-Reflective Coating Surface Treatment to Prevent Defect Generation in Associated Wet Clean
Impedance-Compensating Circuit
Test Bus Architecture for Embedded Ram and Method of Operating Same
Transaction Aligner Microarchitecture
Overvoltage Protection Circuits That Utilize Capacitively Bootstrapped Variable Voltages
Patent:
6,798,629 →
Application:
09/891,906 →
System for Controlling the Delivery of Power to Dc Computer Components Utilizing Phase Shift Regulation
Timer Rollover Handling Mechanism for Traffic Policing
Gate Structures Having Sidewall Spacers Using Selective Deposition and Method of Forming the Same
Patent:
6,740,549 →
Application:
09/927,604 →
Low Voltage, High Current Dc Computer Power System
Integrated Circuit Fifo Memory Devices That Are Divisible into Independent Fifo Queues, and Systems and Methods for Controlling Same
Lead Formation, Assembly Strip Test, and Singulation System
Fifo Memory Devices Having Single Data Rate (Sdr) and Dual Data Rate (Ddr) Capability
High Frequency Power Generator and Related Methods
Multi-Phase Clock Generators That Utilize Differential Signals to Achieve Reduced Setup and Hold Times
Patent:
6,700,425 →
Application:
10/017,628 →
Integrated Circuit Memory Devices Having Asynchronous Flow-Through Capability
Integrated Output Driver Circuits Having Current Sourcing and Current Sinking Characteristics That Inhibit Power Bounce and Ground Bounce
Patent:
6,570,405 →
Application:
10/028,746 →
Multiple Element Rectification Circuit
Patent:
7,110,266 →
Application:
10/030,379 →
Electronically Erasable Memory Cell Using Cmos Technology
Patent:
6,528,842 →
Application:
10/036,326 →
Sram System Having Very Lightly Doped Sram Load Transistors for Improving Sram Cell Stability and Method for Making the Same
Programmable Device and Methods for Disabling a Ring Signal in Response to a Detected Off-Hook Condition
Random Access Memory Architecture and Serial Interface with Continuous Packet Handling Capability
Physical Vapor Deposition Apparatus with Modified Shutter Disk and Cover Ring
Data Memory Address Generation for Time-Slot Interchange Switches
Dual-Layer Deep Ultraviolet Photoresist Process and Structure
Patent:
6,797,456 →
Application:
10/211,493 →
High Frequency Power System and Related Methods
Reducing Layer Separation and Cracking in Semiconductor Devices
Patent:
6,791,197 →
Application:
10/227,772 →
Method for Forming Packaged Semiconductor Device Having Stacked Die
Patent:
6,686,221 →
Application:
10/231,636 →
Integrated Circuit Charge Pumps Having Control Circuits Therein That Inhibit Parasitic Charge Injection from Control Signals
Patent:
6,650,156 →
Application:
10/232,203 →
Method for Generating a Swing Curve and Photoresist Feature Formed Using Swing Curve
Patent:
6,733,936 →
Application:
10/247,877 →
Stress-Relieved Shallow Trench Isolation (Sti) Structure and Method for Forming the Same
Patent:
6,791,155 →
Application:
10/251,550 →
Analogue to Digital Converter
Dual-Wavelength Exposure for Reduction of Implant Shadowing
Patent:
6,913,872 →
Application:
10/262,301 →
Integrated Circuit Inductors Having High Quality Factors
Patent:
6,798,039 →
Application:
10/274,590 →
Electrostatic Discharge Protection Circuit
Patent:
7,102,862 →
Application:
10/283,532 →
Memory Device Layout
Patent:
6,975,527 →
Application:
10/293,176 →
Fifo Memory Devices and Methods of Operating Fifo Memory Devices Having Multi-Port Cache Memory Devices Therein
Patent:
6,754,777 →
Application:
10/307,638 →
Time-Slot Interchange Switches Having Efficient Block Programming and on-Chip Bypass Capabilities and Methods of Operating Same
Patent:
7,266,128 →
Application:
10/314,032 →
Etch Stop Layer for Use in a Self-Aligned Contact Etch
Nitrogen Implementation to Minimize Device Variation
Time-Slot Interchange Switches Having Group-Based Output Drive Enable Control and Group-Based Rate Matching and Output Enable Indication Capability
Patent:
7,260,093 →
Application:
10/324,549 →
Dynamic Phase Tracking Using Edge Detection
Digital Filter
Programmable Oscillator Circuit
Differential Clock Signal Detection Circuit
Method for Power Conversion Using Combining Transformer
Method for Re-Programming a Firmware State Machine During Execution
Fifo Memory Devices That Support All Combinations of Ddr and Sdr Read and Write Modes
Dual Residue Pipelined Analog-to-Digital Converter
Monolithic Clock Generator and Timing/Frequency Reference
Autobias Driving a High Frequency Power System
Signal Timing Adjustment Circuit with External Resistor
Integrated Circuit Memory Devices Having Clock Signal Arbitration Circuits Therein and Methods of Performing Clock Signal Arbitration
Impedance-Matched Output Driver Circuits Having Linear Characteristics and Enhanced Coarse and Fine Tuning Control
Patent:
6,894,529 →
Application:
10/616,272 →
Differential Signaling Transmission Circuit
Clock Signal Generators Having Programmable Full-Period Clock Skew Control and Methods of Generating Clock Signals Having Programmable Skews
Patent:
6,977,539 →
Application:
10/648,090 →
Packaged Semiconductor Device Having Stacked Die
Patent:
6,861,366 →
Application:
10/649,123 →
Dynamic Phase-Locked Loop Circuits and Methods of Operation Thereof
Patent:
7,046,093 →
Application:
10/649,493 →
Delay-Locked Loop (Dll) Integrated Circuits Having High Bandwidth and Reliable Locking Characteristics
Patent:
6,867,627 →
Application:
10/663,624 →
Delayed-Locked Loop with Fine and Coarse Control Using Cascaded Phase Interpolator and Variable Delay Circuit
Patent:
7,046,058 →
Application:
10/671,305 →
Method and Apparatus for Burn-in of Semiconductor Devices
Patent:
7,275,188 →
Application:
10/683,205 →
Data Paths with Receiver Timing Fixable to a Downstream Stage and Methods of Operation Thereof
Patent:
7,134,034 →
Application:
10/686,420 →
Grid Array Microelectronic Packages with Increased Periphery
Patent:
6,930,400 →
Application:
10/689,946 →
End-User Configurable Digital Versatile Disk Menus and Methods for Generating the Same
Patent:
7,646,968 →
Application:
10/706,014 →
Sequential Flow-Control and Fifo Memory Devices That Are Depth Expandable in Standard Mode Operation
Impedance-Matched Output Driver Circuits Having Enhanced Predriver Control
Patent:
6,967,501 →
Application:
10/739,467 →
Edge Accelerated Sense Amplifier Flip-Flop with High Fanout Drive Capability
Patent:
6,924,683 →
Application:
10/741,761 →
Method and Apparatus for an Output Buffer with Dynamic Impedance Control
Patent:
7,126,389 →
Application:
10/765,370 →
Buffer Bypass Circuit for Reducing Latency in Information Transfers to a Bus
Patent:
7,296,109 →
Application:
10/767,001 →
Apparatus and Method for Limiting Data Transmission Rates
Patent:
7,167,997 →
Application:
10/767,964 →
Dynamically Coupled Metrology and Lithography
Patent:
7,349,752 →
Application:
10/773,665 →
Double Data Rate Memory Devices Including Clock Domain Alignment Circuits and Methods of Operation Thereof
Patent:
6,972,998 →
Application:
10/774,904 →
Method for Forming Hybrid Device Gates
Patent:
7,125,775 →
Application:
10/805,124 →
Method for Determining Photoresist Thickness and Structure Formed Using Determined Photoresist Thickness
Patent:
7,235,336 →
Application:
10/808,806 →
Gate Structures Having Sidewall Spacers Using Selective Deposition and Method of Forming the Same
Patent:
7,067,364 →
Application:
10/808,951 →
Fifo Memory Devices Having Multi-Port Cache and Extended Capacity Memory Devices Therein with Retransmit Capability
Precise Voltage/Current Reference Circuit Using Current-Mode Technique in Cmos Technology
Mounting with Auxiliary Bumps
Worldwide Marketing Logistics Network Including Strategically Located Centers for Frequency Programming Crystal Oscillators to Customer Specification
Audio Clocking in Video Applications
Patent:
7,587,131 →
Application:
10/856,436 →
Method and Apparatus for Forwarding Bursty Data
Method for Forming Cmos Structure with Void-Free Dielectric Film
Patent:
7,163,881 →
Application:
10/863,533 →
Method for Forming Shallow Trench Isolation Structure with Deep Oxide Region
Patent:
7,176,104 →
Application:
10/863,540 →
Circuits, Systems, and Methods for Real-Time De-Shuffling of Shuffled Audio Data
Patent:
7,613,615 →
Application:
10/871,287 →
Method for Forming Cmos Device with Self-Aligned Contacts and Region Formed Using Salicide Process
Patent:
7,098,114 →
Application:
10/874,980 →
Multi-Fifo Integrated Circuit Devices That Support Multi-Queue Operating Modes with Enhanced Write Path and Read Path Queue Switching
Patent:
7,120,075 →
Application:
10/876,339 →
Delay-Locked Loop (Dll) Integrated Circuits That Support Efficient Phase Locking of Clock Signals Having Non-Unity Duty Cycles
Patent:
7,109,760 →
Application:
10/880,804 →
Integrated Ddr/Sdr Flow Control Managers That Support Multiple Queues and Mux, Demux and Broadcast Operating Modes
Fifo Memory Devices Having Write and Read Control Circuits That Support X4N, X2N and Xn Data Widths During Ddr and Sdr Modes of Operation
Multi-Subtrate Microstrip to Waveguide Transition
Chip-To-Chip Trench Circuit Structure
Transmission Line Orientation Transition
Delay-Locked Loop (Dll) Integrated Circuits Having Binary-Weighted Delay Chain Units with Built-in Phase Comparators That Support Efficient Phase Locking
Patent:
7,119,591 →
Application:
10/891,919 →
Stress-Relieved Shallow Trench Isolation (Sti) Structure and Method for Forming the Same
Patent:
7,015,116 →
Application:
10/897,601 →
Sequential Flow-Control and Fifo Memory Devices Having Error Detection and Correction Capability with Diagnostic Bit Generation
Patent:
7,246,300 →
Application:
10/912,938 →
Dram Interface Circuits Having Enhanced Skew, Slew Rate and Impedance Control
Photomask with Reduced Elecrostatic Discharge Defects
Patent:
7,419,748 →
Application:
10/925,606 →
Compensated Interdigitated Coupler
Method of Performing Weighted Round-Robin Queue Scheduling Using a Dynamic Link List and Structure for Implementing Same
Multi-Port Memory Cells for Use in Fifo Applications That Support Data Transfers Between Cache and Supplemental Memory Arrays
Ripple Counter Circuits in Integrated Circuit Devices Having Fast Terminal Count Capability and Methods of Operating the Same
Patent:
7,092,479 →
Application:
10/931,699 →
Scan Chain Registers That Utilize Feedback Paths Within Latch Units to Support Toggling of Latch Unit Outputs During Enhanced Delay Fault Testing
Multi-Bank Integrated Circuit Memory Devices Having High-Speed Memory Access Timing
Patent:
7,110,321 →
Application:
10/935,518 →
Interrupt Coalescer for Dma Channel
Patent:
7,478,186 →
Application:
10/939,536 →
System and Method of Scheduling Computing Threads
Waveform Independent High Frequency Power System
Optimal Buffering and Scheduling Strategy for Smooth Reverse in a Dvd Player or the Like
Telecine Conversion Detection for Progressive Scan Playback
Method and Apparatus for Font Processing
Stacked Paddle Micro Leadframe Package
Patent:
7,166,905 →
Application:
10/958,697 →
Self-Aligned Contact Structure and Process for Forming Self-Aligned Contact Structure
Patent:
7,037,774 →
Application:
10/970,074 →
Controlling a Clock Divider by Selecting a Preset Value
Patent:
7,308,596 →
Application:
10/975,219 →
Programmable Clock Drivers That Support Crc Error Checking of Configuration Data During Program Restore Operations
Patent:
7,196,562 →
Application:
10/979,979 →
Process for Forming Cmos Devices Using Removable Spacers
Patent:
7,544,556 →
Application:
10/986,636 →
Automated Ball Mounting System with Solder Ball Testing
Nitrogen Implementation to Minimize Device Variation
Systems and Methods for Monitoring and Controlling Binary State Devices Using a Memory Device
Method and Apparatus for Clock Generation
Patent:
7,176,738 →
Application:
10/993,657 →
Memory Array Bit Line Coupling Capacitor Cancellation
Output Drive Circuit That Accommodates Variable Supply Voltages
Scheduler for a Multiprocessing Computing System
Integrated Circuit Package Encapsulating a Hermetically Sealed Device
Method and Apparatus for Switching, Merging, and Demerging Data Between Data Communication Locations
Patent:
7,701,957 →
Application:
11/040,063 →
Mark/Re-Read and Mark/Re-Write Operations in a Multi-Queue First-in First-Out Memory System
Synchronization of Active Flag and Status Bus Flags in a Multi-Queue First-in First-Out Memory System
Multiple Counters to Relieve Flag Restriction in a Multi-Queue First-in First-Out Memory System
Status Bus Accessing Only Available Quadrants During Loop Mode Operation in a Multi-Queue First-in First-Out Memory System
Interleaving Memory Blocks to Relieve Timing Bottleneck in a Multi-Queue First-in First-Out Memory System
Partial Packet Write and Write Data Filtering in a Multi-Queue First-in First-Out Memory System
Multi-Queue Address Generator for Start and End Addresses in a Multi-Queue First-in First-Out Memory System
Self-Timed Multiple Blanking for Noise Suppression During Flag Generation in a Multi-Queue First-in First-Out Memory System
Method and Apparatus for Buffer with Programmable Skew
Patent:
7,268,599 →
Application:
11/050,009 →
Penlight and Touch Screen Data Input System and Method for Flat Panel Displays
Electrostatic Discharge and Electrical Overstress Protection Circuit
Patent:
7,522,395 →
Application:
11/063,703 →
Memory Cell with Reduced Soft Error Rate
Patent:
7,214,990 →
Application:
11/063,704 →
In-Situ Monitor of Process and Device Parameters in Integrated Circuits
External Observation and Control of Data in a Computing Processor
Patent:
7,353,345 →
Application:
11/075,049 →
Multi-Queue Fifo Memory Devices That Support Flow-Through of Write and Read Counter Updates Using Multi-Port Flag Counter Register Files
Patent:
7,447,812 →
Application:
11/080,704 →
Monolithic Clock Generator and Timing/Frequency Reference
Transconductance and Current Modulation for Resonant Frequency Control and Selection
Intelligent Caching Scheme for Streaming File Systems
Integrated Circuits and Methods with Statistics-Based Input Data Signal Sample Timing
Patent:
7,508,893 →
Application:
11/092,032 →
Method for forming photomask having test patterns in blading areas
Patent:
7,378,289 →
Application:
11/100,144 →
Integrated Circuits and Methods with Transmit-Side Data Bus Deskew
Patent:
7,571,337 →
Application:
11/136,056 →
On-Chip Interface Trap Characterization and Monitoring
Patent:
7,472,322 →
Application:
11/141,223 →
In-Situ Monitor of Process and Device Parameters in Integrated Circuits
Time Slot Interchange Switch with Bit Error Rate Testing
Multi-Queue Fifo Memory Devices That Support a Backed-Off Standard Mode of Operation and Methods of Operating Same
Patent:
7,392,354 →
Application:
11/144,881 →
Systems and Methods for Detecting a Change in a Sequence of Interlaced Data Fields Generated from a Progressive Scan Source
Patent:
7,420,626 →
Application:
11/167,682 →
Circuits and Methods for Detecting 2:2 Encoded Video and Systems Utilizing the Same
Patent:
7,450,184 →
Application:
11/167,756 →
Circuits and Methods for Deinterlacing Video Display Data and Systems Using the Same
Patent:
7,522,214 →
Application:
11/167,877 →
Systems and Methods for Display Object Edge Detection and Pixel Data Interpolation in Video Processing Systems
Patent:
7,414,671 →
Application:
11/172,323 →
High Voltage Input Buffer
Patent:
7,382,159 →
Application:
11/179,071 →
High Speed Mosfet Output Driver
Patent:
7,227,400 →
Application:
11/179,072 →
Apparatus and Method for Matrix Memory Switching Element
Voltage Sensing Circuit
Patent:
7,259,614 →
Application:
11/187,680 →
Method and Apparatus for Predictive Switching
Systems and Methods for Reducing Noise During Video Deinterlacing
Patent:
7,538,824 →
Application:
11/206,402 →
Impedance-Matched Output Driver Circuits Having Enhanced Predriver Control
Patent:
7,053,661 →
Application:
11/207,370 →
Integrated Circuit Memory Devices Having Asynchronous Flow-Through Capability
Patent:
7,093,083 →
Application:
11/207,552 →
Clock Signal Generators Having Programmable Full-Period Clock Skew Control
Self-Biased Electrostatic Discharge Protection Method and Circuit
Patent:
7,408,751 →
Application:
11/229,195 →
Low Jitter Frequency Synthesizer
Patent:
7,274,231 →
Application:
11/229,472 →
Frequency Controller for a Monolithic Clock Generator and Timing/Frequency Reference
Frequency Calibration for a Monolithic Clock Generator and Timing/Frequency Reference
Low-Latency Start-Up for a Monolithic Clock Generator and Timing/Frequency Reference
Low Power Output Driver
Over Driving Pin Function Selection Method and Circuit
Patent:
7,675,790 →
Application:
11/239,907 →
Method and Apparatus for Generic Interface, Packet Cut-Through, Overbooking, Queue Concatenation, and Logical Identification Priority for a System Packet Interface Device
Locked-Loop Integrated Circuits Having Speed Tracking Circuits Therein
Patent:
7,239,188 →
Application:
11/264,111 →
Auto-Adaptive Digital Phase-Locked Loop for Large Frequency Multiplication Factors
Data Output Clock Selection Circuit for Quad-Data Rate Interface
Minimizing Timing Skew Among Chip Level Outputs for Registered Output Signals
Method and Apparatus for Pre-Clocking
Fast Parity Scan of Memory Arrays
Patent:
7,565,597 →
Application:
11/315,971 →
Over-Voltage Tolerant Multifunction Input Stage
Patent:
7,321,238 →
Application:
11/317,066 →
Thin Film Resistor Structure
Over-Voltage Tolerant Esd Protection Circuit
Patent:
7,518,844 →
Application:
11/352,496 →
Phase-Locked Loop Circuits with Current Mode Loop Filters
Negative Voltage Coefficient Resistor and Method of Manufacture
Patent:
7,642,892 →
Application:
11/373,374 →
Complementary Output Inverter
Error Management System and Method for a Packet Switch
Patent:
7,747,904 →
Application:
11/383,121 →
System and Method of Constructing Data Packets in a Packet Switch
Patent:
7,817,652 →
Application:
11/383,150 →
Packet Processing in a Packet Switch with Improved Output Data Distribution
Patent:
7,596,142 →
Application:
11/383,165 →
Inductor and Capacitor-Based Clock Generator and Timing/Frequency Reference
Integrated Clock Generator and Timing/Frequency Reference
Discrete Clock Generator and Timing/Frequency Reference
Core Clock Alignment Circuits That Utilize Clock Phase Learning Operations to Achieve Accurate Clocking of Data Derived from Serial Data Streams Having Different Relative Skews
Patent:
7,571,267 →
Application:
11/389,748 →
Packet Processors Having Multi-Functional Range Match Cells Therein
Patent:
7,298,636 →
Application:
11/393,284 →
Packet Processors Having Comparators Therein That Determine Non-Strict Inequalities Between Applied Operands
Patent:
7,825,777 →
Application:
11/393,489 →
System and Method for Detecting Single Event Latchup in Integrated Circuits
System and Method for Integrated Circuit Charge Recycling
Patent:
7,414,460 →
Application:
11/395,061 →
Logic Soft Error Rate Prediction and Improvement
Packet Processing Switch and Methods of Operation Thereof
Packet Processing Switch and Methods of Operation Thereof
Gate Structures Having Sidewall Spacers Formed Using Selective Deposition
Patent:
7,375,392 →
Application:
11/395,818 →
Dual Port Memory Cell with Reduced Coupling Capacitance and Small Cell Size
System and Method for Arbitration in a Packet Switch
Patent:
7,684,431 →
Application:
11/407,321 →
Method and Apparatus for an Output Buffer with Dynamic Impedance Control
Patent:
8,120,405 →
Application:
11/419,454 →
System and Method for Arbitration Using Availability Signals
Patent:
8,289,989 →
Application:
11/419,572 →
System and Method for Arbitration of Multicast Data Packets Using Holds
Patent:
7,782,780 →
Application:
11/420,837 →
Method and Apparatus for Overbooking on Fifo Memory
Patent:
7,636,367 →
Application:
11/421,330 →
System and Method for Round Robin Arbitration
Patent:
7,706,387 →
Application:
11/421,415 →
Amplitude and Bandwidth Pre-Emphasis of a Data Signal
Patent:
7,327,814 →
Application:
11/422,252 →
Comparator with Amplitude and Time Hysteresis
Patent:
7,714,620 →
Application:
11/422,381 →
Method for Forming Cmos Device with Self-Aligned Contacts and Region Formed Using Salicide Process
Patent:
7,582,567 →
Application:
11/424,333 →
Current Mode Driver with Constant Voltage Swing
Patent:
7,405,594 →
Application:
11/424,779 →
Built-In-Redundancy Analysis Using Ram
Patent:
7,536,614 →
Application:
11/427,322 →
Method and Apparatus for Fast Pll Initialization
Patent:
8,265,219 →
Application:
11/428,071 →
Vco Digital Range Selection
Input Termination Circuitry with High Impedance at Power Off
Die Seal with Reduced Noise Coupling
Patent:
7,560,800 →
Application:
11/459,820 →
System and Method for Testing a Clock Circuit
Patent:
7,750,618 →
Application:
11/459,889 →
Multiphase Clock Generator
Patent:
7,545,188 →
Application:
11/462,627 →
Method and Apparatus for Improved Efficiency in Protocols Using Character Coding
Patent:
7,602,318 →
Application:
11/462,973 →
Dram Interface Circuits That Support Fast Deskew Calibration and Methods of Operating Same
Low Variation Voltage Output Differential for Differential Drivers
Method for Deterministic Timed Transfer of Data with Memory Using a Serial Interface
Method of Handling Flow Control in Daisy-Chain Protocols
Method for Improved Single Event Latch Up Resistance in an Integrated Circuit
Delay Chain Integrated Circuits Having Binary-Weighted Delay Chain Units with Built-in Phase Comparators Therein
Patent:
7,279,938 →
Application:
11/532,657 →
Solid State Electrochemical Gas Sensor and Method for Fabricating Same
Method and Apparatus with Power and Ground Strips for Connecting to Decoupling Capacitors
Patent:
7,329,958 →
Application:
11/536,210 →
Low Power Logic Output Buffer
Error Reduction in a Digital-to-Analog (Dac) Converter
Package Substrate with Inserted Discrete Capacitors
Phase Difference Detector Having Concurrent Fine and Coarse Capabilities
Input Termination for Delay Locked Loop Feedback with Impedance Matching
Common Access Ring System
Common Access Ring/Sub-Ring System
Using a Delay Clock to Optimize the Timing Margin of Sequential Logic
Method and Apparatus for Clock Generation
Patent:
7,602,226 →
Application:
11/618,545 →
Modular Distributive Arithmetic Logic Unit
Method and Apparatus for Cross-Point Detection
Patent:
7,671,602 →
Application:
11/626,594 →
Electrical Overstress (Eos) and Electrostatic Discharge (Esd) Protection Circuit and Method of Use
Patent:
7,706,113 →
Application:
11/668,360 →
Method and Structure to Support System Resource Access of a Serial Device Implementing a Lite-Weight Protocol
Hardware-Based Concurrent Direct Memory Access (DMA) Engines On Serial Rapid Input/Output SRIO Interface
Rapid Input/Output Doorbell Coalescing to Minimize Cpu Utilization and Reduce System Interrupt Latency
Multi-Bus Structure for Optimizing System Performance of a Serial Buffer
Phase Locked Loop and Delay Locked Loop with Chopper Stabilized Phase Offset
Circuit Structure with Multifunction Circuit Cover
Simple Technique for Reduction of Gain in a Voltage Controlled Oscillator
Input Clock Detection Circuit for Powering Down a Pll-Based System
High-Speed, Low-Power Level Shifter for Mixed Signal-Level Environments
Tunable Optical Oscillator
Patent:
7,436,865 →
Application:
11/713,466 →
Method and Apparatus for Ground Bounce and Power Supply Bounce Detection
Patent:
7,560,936 →
Application:
11/739,459 →
Method and Apparatus for Adjusting Pll and/or Dll Timing Offsets
Patent:
7,956,693 →
Application:
11/739,546 →
Processing Switch for Orthogonal Frequency Division Multiplexing
Patent:
7,693,040 →
Application:
11/743,080 →
Composite Membranes and Methods for Making Same
Digitally Controlled System on-Chip (Soc) Clock Generator
Patent:
7,573,303 →
Application:
11/781,452 →
Folded-Cascode Amplifier with Adjustable Continuous Time Equalizer
Patent:
7,683,720 →
Application:
11/781,629 →
Behavioral Modeling of High Speed Differential Signals Based on Physical Characteristics
Transconductance and Current Modulation for Resonant Frequency Control and Selection
Monolithic Clock Generator and Timing/Frequency Reference
Output Drive Circuit That Accommodates Variable Supply Voltages
Multi-Terminal Harmonic Oscillator Integrated Circuit with Frequency Calibration and Frequency Configuration
Frequency Calibration for a Monolithic Clock Generator and Timing/Frequency Reference
Method and Apparatus for Packet Cut-Through
Patent:
8,036,216 →
Application:
11/857,249 →
Method and Apparatus for Queue Concatenation
Patent:
8,064,472 →
Application:
11/857,326 →
Method and Apparatus for Logical Identification Priority
Patent:
7,505,468 →
Application:
11/857,361 →
Adaptive Decision Feedback Equalizer for High Data Rate Serial Link Receiver
Patent:
7,916,779 →
Application:
11/858,834 →
Ddr Memory System for Measuring a Clock Signal by Identifying a Delay Value Corresponding to a Changed Logic State During Clock Signal Transitions
Patent:
7,886,176 →
Application:
11/860,110 →
Methods and Circuits for Ddr-2 Memory Device Read Data Resynchronization
Patent:
7,558,151 →
Application:
11/860,910 →
Integrated Circuit Memory Systems Having Write-Back Buffers Therein That Support Read-Write-Modify (Rwm) Operations Within High Capacity Memory Devices
Patent:
7,739,460 →
Application:
11/861,399 →
Clock Generator and Method for Providing Reliable Clock Signal Using Array of Mems Resonators
Patent:
7,941,723 →
Application:
11/861,869 →
Clock Generator with Self-Bias Bandwidth Control
Patent:
7,586,347 →
Application:
11/862,653 →
Serial Buffer Supporting Virtual Queue to Physical Memory Mapping
Multi-Function Queue to Support Data Offload, Protocol Translation and Pass-Through Fifo
Adaptive Interrupt on Serial Rapid Input/Output (Srio) Endpoint
Method and Apparatus for Pre-Clocking
Patent:
7,629,816 →
Application:
11/872,027 →
Error Correction Code System and Method
Patent:
8,069,392 →
Application:
11/873,357 →
Voltage-To-Current Converter
Method for Reliable Injection of Deterministic Jitter for High Speed Transceiver Simulation
Package with Improved Connection of a Decoupling Capacitor
Common Mode Voltage Extraction Circuit
Methods and Systems for Providing Variable Clock Rates and Data Rates for a Serdes
Digital Spread Spectrum Method Based on Precise Phase Delta-Sigma Algorithm
Method for Binary Clock and Data Recovery for Fast Acquisition and Small Tracking Error
Low-Latency Start-Up for a Monolithic Clock Generator and Timing/Frequency Reference
Low Power Output Driver
Automated Ball Mounting Process with Solder Ball Testing
Semiconductor Die and Method for Forming a Semiconductor Die Having Power and Ground Strips That Are Oriented Diagonally
Patent:
7,800,236 →
Application:
11/935,241 →
Output Slew Rate Control in Low Voltage Differential Signal (Lvds) Driver
Phase Step Clock Generator
Patent:
7,737,739 →
Application:
11/955,340 →
Packet Switch with Port Route Tables
Patent:
8,040,888 →
Application:
11/958,313 →
Look-Ahead Built-in Self Tests
Patent:
7,877,657 →
Application:
11/960,618 →
Spread Spectrum Clock and Reference Signal Generator
Integrated Circuit Systems Having Processor-Controlled Clock Signal Generators Therein That Support Efficient Power Management
Combined Touch Sensor and Led Driver with N-Type Mosfet Protecting Touch Sensor
High Speed Hybrid Structure Counter Having Synchronous Timing and Asynchronous Counter Cells
Systems and Methods for Clean Dqs Signal Generation in Source-Synchronous DDR2 Interface Design
Phase and Frequency Detector with Zero Static Phase Error
Digitally Compensated Highly Stable Holdover Clock Generation Techniques Using Adaptive Filtering
Buffered Dram
Control Voltage Generator for a Clock, Frequency Reference, and Other Reference Signal Generator
Clock, Frequency Reference, and Other Reference Signal Generator with a Controlled Quality Factor
Automated Clock Relationship Detection
Discrete Clock Generator and Timing/Frequency Reference
Integrated Clock Generator and Timing/Frequency Reference
Merged-Filter Multiplexer
Chip Mounting with Flowable Layer
Method To Support Flexible Data Transport On Serial Protocols
Protocol Translation in a Serial Buffer
Serial Buffer to Support Request Packets with Out of Order Response Packets
Method to Support Lossless Real Time Data Sampling and Processing on Rapid I/O End-Point
Content Driven Packet Switch
Circuit Board Assembly and Packaged Integrated Circuit Device with Power and Ground Channels
Patent:
7,847,404 →
Application:
12/052,234 →
High Frequency Fractional-N Divider
Phase-Locked Loop
Method and Apparatus for Dqs Postamble Detection and Drift Compensation in a Double Data Rate (Ddr) Physical Interface
Method and Apparatus for Analog Smooth Switch in Vco Loading Control
Patent:
7,834,708 →
Application:
12/112,362 →
Voltage Reference and Supply Voltage Level Detector Circuits Using Proportional to Absolute Temperature Cells
Patent:
8,072,259 →
Application:
12/112,933 →
Method and Apparatus for Externally Aided Self Adjusting Real Time Clock
Patent:
8,392,001 →
Application:
12/114,754 →
Compression of Baseband Signals in Base Transceiver Systems
Compression of Signals in Base Transceiver Systems
Method and Apparatus for Self Gate Pumped Nmos High Speed Switch
Patent:
7,741,897 →
Application:
12/129,545 →
Current Control Mechanism for Low Voltage Applications
Patent:
7,760,781 →
Application:
12/150,615 →
Signal Amplitude Distortion Within an Integrated Circuit
Integrated Circuit Communication Self-Testing
Programmable Duty Cycle Distortion Generation Circuit
Electrostatic Discharge Event Protection for an Integrated Circuit
Method of Processing Signal Data with Corrected Clock Phase Offset
Small Pitch Ball Grid Array of a Package Assembly for Use with Conventional Burn-in Sockets
Multi-Package Slot Array
Multiple Frequency Synchronized Phase Clock Generator
Impedance Matching Logic
Asynchronous Biphase Mark Signal Receivers and Methods of Operating Same
Patent:
8,023,594 →
Application:
12/171,612 →
Voltage and Temperature Invariant Current Setting Circuit
Patent:
8,008,904 →
Application:
12/184,189 →
Systems and Methods for Power Management in Electronic Devices
Power Reduction Technique for Buffered Crossbar Switch
Patent:
7,907,625 →
Application:
12/185,716 →
Lead Frame Package
Memory Register Having an Integrated Delay-Locked Loop
Method for Synchronization of Peripherals with a Central Processing Unit in an Embedded System
Managing Transmit Jitter for Multi-Format Digital Audio Transmission
Low-Loss Impedance-Matched Source-Follower for Repeating or Switching Signals on a High Speed Link
Reduced Power Differential Type Termination Circuit
Integrated Circuit Comparators Having Improved Input Resolution and Methods of Operating Same
Patent:
7,728,632 →
Application:
12/211,326 →
Voltage-Mode Line Driving Circuit Having Adaptive Impedance Matching
Synchronous De-Skew with Programmable Latency for Multi-Lane High Speed Serial Interface
Digital-To-Analog Converter
Linear Monotonic Delay Chain Circuit
Packet Switch with Configurable Virtual Channels
Patent:
7,974,278 →
Application:
12/234,877 →
Methods of Forming Multi-Chip Semiconductor Substrates
Patent:
7,871,857 →
Application:
12/240,292 →
Electronic Display with Array Context-Sensitive Search (Acs) Technology
Patent:
8,179,372 →
Application:
12/240,872 →
Method and Apparatus for Active Line Interface Isolation
Patent:
8,154,880 →
Application:
12/253,891 →
Esd Protection Circuit for Inside a Power Pad or Input/Output Pad
Oscillators Having Reactance-Adjustable Frequency Control
Packet Latency Based Arbitration Technique for a Packet Switch
Patent:
8,014,288 →
Application:
12/266,377 →
Look-Ahead Built-in Self Tests with Temperature Elevation of Functional Elements
Patent:
8,028,211 →
Application:
12/268,854 →
Sequential Decoding of Progressive Coded Jpegs
Field Programmable Application Specific Integrated Circuit with Programmable Logic Array and Method of Designing and Programming the Programmable Logic Array
Old Virtual Queues Technique for Routing Data Packets in a Packet Switch
Patent:
8,081,646 →
Application:
12/328,953 →
Packet Switch with Configurable Bandwidth Allocation Precision
Patent:
7,796,629 →
Application:
12/331,372 →
Method and Apparatus for Fail-Safe Start-Up Circuit for Subthreshold Current Sources
Patent:
8,316,245 →
Application:
12/333,149 →
Overclocking with Phase Selection
Low Power Output Driver
Inductor and Capacitor-Based Clock Generator and Timing/Frequency Reference
Clock Circuit with Harmonic Frequency Detector
Patent:
7,786,763 →
Application:
12/346,764 →
Methods of Forming Microelectronic Packaging Substrates Having Through-Substrate Vias Therein
Patent:
7,842,613 →
Application:
12/349,677 →
Methods of Forming Packaged Micro-Electromechanical Devices
Patent:
7,955,885 →
Application:
12/351,020 →
Spread Spectrum Clock Generation Technique for Imaging Applications
Patent:
8,164,367 →
Application:
12/354,453 →
Thermo-Decoder Circuit
Clock Circuit for Reducing Long Term Jitter
Patent:
7,816,959 →
Application:
12/391,105 →
Thin-Film Bulk Acoustic Resonators Having Perforated Bodies That Provide Reduced Susceptibility to Process-Induced Lateral Dimension Variations
Micro-Electromechanical Devices Having Variable Capacitors Therein That Compensate for Temperature-Induced Frequency Drift in Acoustic Resonators
Method and Apparatus for Ground Bounce and Power Supply Bounce Detection
Patent:
8,008,927 →
Application:
12/405,846 →
Method for Measuring Phase Locked Loop Bandwidth Parameters for High-Speed Serial Links
Multi-Touch Touch Screen with Single-Layer Ito Bars Arranged in Parallel
Computing System with Detachable Touch Screen Device
Patent:
8,149,224 →
Application:
12/431,693 →
Monolithic Clock Generator and Timing/Frequency Reference
Non-Linear Crystal Oscillator Capacitive Load Circuits
Patent:
7,990,226 →
Application:
12/463,749 →
Push-Pull Spread Spectrum Clock Signal Generator
Patent:
8,284,816 →
Application:
12/476,177 →
Method for Forming Integrated Circuit Device Using Cell Library with Soft Error Resistant Logic Cells
Patent:
7,921,400 →
Application:
12/478,734 →
Low Power Clock and Data Recovery Phase Interpolator
Novel Regulation Scheme for a Charge Pump
Methods and Apparatuses for Incremental Bandwidth Changes Responsive to Frequency Changes of a Phase-Locked Loop
Apparatus and Method for Detecting the Loss of an Input Clock Signal for a Phase-Locked Loop
Method and Apparatus for Placing Quartz Saw Devices Together with Clock/Oscillator
Patent:
8,395,247 →
Application:
12/493,510 →
Charge Pump Linearization Technique for Delta-Sigma Fractional-N Synthesizers
Ac Coupled Clock Receiver with Common-Mode Noise Rejection
Patent:
8,693,557 →
Application:
12/497,485 →
Interleaved/All-Phase Mode Switched Pwm System
Thin-Film Bulk Acoustic Resonators Having Perforated Resonator Body Supports That Enhance Quality Factor
Patent:
8,106,724 →
Application:
12/508,257 →
Alternating, Complementary Conductive Element Pattern for Multi-Touch Sensor
Audio Clocking in Video Applications
Holdover Circuit for Phase-Lock Loop
Patent:
8,018,289 →
Application:
12/544,201 →
Method and Apparatus for Compression of Configuration Bitstream of Field Programmable Logic
High Voltage Switch Utilizing Low Voltage Mos Transistors with High Voltage Breakdown Isolation Junctions
Method and Apparatus for Auto-Frequency Calibration for Multi-Band Vco
Patent:
8,138,845 →
Application:
12/561,039 →
Method and Apparatus for Frequency Compensation for Multi-Band Vco
Patent:
8,093,957 →
Application:
12/561,166 →
Apparatuses and Methods for a Scr-Based Clamped Electrostatic Discharge Protection Device
Technique to Reduce Clock Recovery Amplitude Modulation in High-Speed Serial Transceiver
Method and Apparatus of Ate Ic Scan Test Using Fpga-Based System
High Speed Chip Screening Method Using Delay Locked Loop
Apparatuses and Methods for a Level Shifter with Reduced Shoot-Through Current
Multi-Band Clock Generator with Adaptive Frequency Calibration and Enhanced Frequency Locking
Patent:
8,509,372 →
Application:
12/626,256 →
Method and Apparatus for Programmable Buffer with Dynamic Allocation to Optimize System Throughput with Deadlock Avoidance on Switches
Patent:
8,320,392 →
Application:
12/639,554 →
Method and Apparatus for Adaptive Buffer Management for Traffic Optimization on Switches
Patent:
8,254,399 →
Application:
12/639,887 →
Method and Apparatus for Glitch-Free Switching of Multiple Phase Clock
Patent:
8,680,910 →
Application:
12/640,750 →
Analog/Digital or Digital/Analog Conversion System Having Improved Linearity
High Speed Switch with Data Converter Physical Ports
Equalization System with Stabilized Peaking Gain for a Communication System
Circuit Including Current-Mode Logic Driver with Multi-Rate Programmable Pre-Emphasis Delay Element
Systems, Devices, and Methods for Providing Backup Power to a Load
Method and Apparatus for Selective Packet Discard
Patent:
8,238,339 →
Application:
12/712,477 →
Method and Apparatus for Dynamic Traffic Management with Packet Classification
Patent:
8,325,723 →
Application:
12/712,516 →
Method and Apparatus for Congestion and Fault Management with Time-to-Live
Patent:
8,902,765 →
Application:
12/712,560 →
Thin-Film Bulk Acoustic Resonators Having Multi-Axis Acoustic Wave Propagation Therein
Patent:
8,368,487 →
Application:
12/713,940 →
Apparatuses and Methods for Multiple-Output Comparators and Analog-to-Digital Converters
Methods and Apparatuses for Cordic Processing
Methods and Apparatuses for Flexible and High Performance Digital Signal Processing
Clock, Frequency Reference, and Other Reference Signal Generator with Frequency Stability Over Temperature Variation
Apparatuses and Methods for Physical Layouts of Analog-to-Digital Converters
Energy Conversion Device with Support Member Having Pore Channels
Current Control Mechanism for Low Voltage Applications
Apparatuses and Methods for a Voltage Level Shifting
High Speed Switch With Data Converter Physical Ports And Processing Unit
Method and Apparatus for Unified Final Buffer with Pointer-Based and Page-Based Scheme for Traffic Optimization
Patent:
8,850,089 →
Application:
12/818,767 →
Method And Apparatus To Optimize Class Of Service Under Multiple VCs With Mixed Reliable Transfer And Continuous Transfer Modes
Patent:
8,571,050 →
Application:
12/818,805 →
5V Tolerant Circuit for Cml Transceiver in Ac-Couple
Semiconductor Resonators with Electromagnetic and Environmental Shielding and Methods of Forming Same
Patent:
8,164,159 →
Application:
12/838,158 →
Dynamic phase tracking using edge detection that employs an edge counter
Methods and Apparatuses for Clock Domain Crossing
Systems, Apparatuses and Methods for Dynamic Voltage and Frequency Control of Components Used in a Computer System
Transmission of Multiprotocol Data in a Distributed Antenna System
System and Method for Formatting Symbols in a Data Stream
Patent:
8,379,771 →
Application:
12/876,988 →
System and Method for Communication Handshaking Between a Master Processors and a Slave Processor
Method and Apparatus for Implementation of Pll Minimum Frequency via Voltage Comparison
Patent:
8,513,992 →
Application:
12/879,995 →
Slew Rate-Variation Based Driver Equalization for Far-End Crosstalk Cancellation
Patent:
8,493,833 →
Application:
12/885,049 →
Method and Apparatus for Duty-Cycle Correction with Reduced Current Consumption
Patent:
8,324,948 →
Application:
12/889,254 →
Audio Clocking in Video Applications
Method and Apparatus for Implementation of High Order MASH by Reuse of Single Stage MASH
Patent:
8,732,224 →
Application:
12/889,331 →
Method and Apparatus for a configurable packet routing, buffering and scheduling scheme to optimize throughput with deadlock prevention in SRIO-to-PCIe Bridges
Patent:
9,143,346 →
Application:
12/916,568 →
Method and Apparatus for a configurable packet routing, buffering and scheduling scheme to optimize throughput with deadlock prevention in SRIO-to-PCIe Bridges
Patent:
8,949,501 →
Application:
12/916,574 →
Method and Apparatus for a configurable packet routing, buffering and scheduling scheme to optimize throughput with deadlock prevention in SRIO-to-PCIe Bridges
Patent:
8,730,983 →
Application:
12/916,580 →
Flash Analog-to-Digital Converter
Flip Chip Bump Array with Superior Signal Performance
Self-Adaptive Current-Mode-Control Circuit for a Switching Regulator
Voltage Level Shifting Apparatuses and Methods
Methods and Apparatuses for Combined Frequency Compensation and Soft Start Processes
Combinations of Current Feedback for Frequency Compensation, Overload Detection, and Super Overload Detection in Switching Power Converters
Proportional Area Weighted Sensor for Two-Dimensional Locations on a Touch Screen
Method to Improve Performance of a Proportional Area Weighted Sensor for Two-Dimensional Locations on a Touch Screen
Touch Sensor Having Improved Edge Response
Method and Apparatus for Novel Adaptive Equalization Technique For Serializer/Deserializer Links
Patent:
10,063,397 →
Application:
12/976,853 →
Emi Mitigation of Power Converters by Modulation of Switch Control Signals
Controller for Secondary Side Control of a Switch, Power Converter, and Related Synchronous Rectification Control Method
Switched-Capacitor Pipeline Adc Stage
System and Method for Improving the Timestamp Precision in a Precision Time Protocol (Ptp) Device
Patent:
8,949,448 →
Application:
13/015,483 →
Methods of Forming Microdevice Substrates Using Double-Sided Alignment Techniques
Patent:
8,283,256 →
Application:
13/034,004 →
Methods of Forming Micro-Electromechanical Resonators Using Passive Compensation Techniques
Patent:
8,501,515 →
Application:
13/035,148 →
Apparatuses and Methods for Reducing Power in Driving Display Panels
Mechanical Means for Providing Haptic Feedback in Connection with Capacitive Sensing Mechanisms
Low on-Resistance Power Transistor Having Transistor Stripes
Apparatuses and Methods for Reducing Errors in Analog to Digital Converters
Autonomous Controlled Headroom Low Dropout Regulator For Single Inductor Multiple Output Power Supply
Methods of Packaging Microelectromechanical Resonators
Patent:
8,426,233 →
Application:
13/077,312 →
Ad Converter
Method and Apparatus for An Equalized On-Die Termination (ODT) Circuit
Method and Apparatus for a Low Power Ac on-Die-Termination (Odt) Circuit
Digital Signal Generator
Method of Gain Calibration of an Adc Stage and an Adc Stage
Switched-Capacitor Pipeline Stage
Pipelined Adc Calibration
Power Management Integrated Circuit Using a Flexible Script-Based Configurator and Method for Power Management
Microelectromechanical Resonators with Thermally-Actuated Frequency Tuning Beams
Patent:
8,633,635 →
Application:
13/174,082 →
Microelectromechanical Resonators with Passive Frequency Tuning Using Built-in Piezoelectric-Based Varactors
Patent:
8,575,819 →
Application:
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Periodic Signal Generators Having Microelectromechanical Resonators Therein That Support Generation of High Frequency Low-TCF Difference Signals
Patent:
8,742,854 →
Application:
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Compression of Baseband Signals in Base Transceiver Systems
Low Noise Variable Gain Amplifier Utilizing Variable Feedback Techniques with Constant Input/Output Impedance
Power Management System and Method for Peripheral Devices
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Application:
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Compression of Baseband Signals in Base Transceiver System Interfaces
Compression of Baseband Signals in Base Transceiver System Radio Units
Compression of Baseband Signals in Base Transceiver System Processors
Method and Apparatus for a Transmission Gate for Multi-GB/s Application
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Publication:
US 2018/0350878
Method and Apparatus for Reduction of Communications Media Energy Consumption
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9,240,892 →
Application:
13/244,586 →
Method and Apparatus for Channel Equalization in High Speed S-Rio Based Communication Systems
Patent:
8,842,721 →
Application:
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Third Overtone Crystal-Based Oscillators Having Tunable All-Pass Rc Filters Therein
Patent:
8,519,800 →
Application:
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Apparatus and Method for a Switching Power Converter
Frequency Synthesizers with Dynamic Calibration Intervals
Patent:
8,552,804 →
Application:
13/249,659 →
Microelectromechanical Resonators Having Resistive Heating Elements Therein Configured to Provide Frequency Tuning Through Convective Heating of Resonator Bodies
Patent:
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Application:
13/250,560 →
Apparatus, System, and Method for Detecting a Foreign Object in an Inductive Wireless Power Transfer System
Reconfigurable Divider Circuits with Hybrid Structure
Patent:
8,542,040 →
Application:
13/285,103 →
Integrated Circuit Devices Using Analog Dividers
Patent:
8,754,719 →
Application:
13/334,535 →
Frequency Domain Compression in a Base Transceiver System
Apparatuses, Systems, and Methods for a Monotonic Transfer Function in Wireless Power Transfer Systems
Methods of Testing Packaged Thin-Film Piezoelectric-on-Semiconductor Microelectromechanical Resonators Having Hermetic Seals
Patent:
8,638,178 →
Application:
13/407,484 →
Composite Membrane with Integral Rim
Test Assembly for Verifying Heat Spreader Grounding in a Production Test
Systems and Methods for Peak Detection in Automatic Gain Control Circuits in High-Speed Wireline Communications
Systems and Methods for Adaptive Equalization Control for High-Speed Wireline Communications
Method and Apparatus for Using Tester Channel as Device Power Supply
Patent:
9,442,167 →
Application:
13/422,725 →
Fractional-N Dividers Having Divider Modulation Circuits Therein with Segmented Accumulators
Patent:
8,559,587 →
Application:
13/425,761 →
Apparatuses and Methods Responsive to Output Variations in Voltage Regulators
Apparatuses Having Different Modes of Operation for Inductive Wireless Power Transfer and Related Method
Apparatuses and Methods for Providing Quantized Coefficients for Video Encoding
Matched Feedback Amplifier with Improved Linearity
Periodic Signal Generators Having Microelectromechanical Resonators Therein That Support Surface Wave and Bulk Acoustic Wave Modes of Operation with Different Temperature Coefficients of Frequency
Patent:
8,680,931 →
Application:
13/435,817 →
High Accuracy Temperature Sensor
Apparatus, System, and Method for Detecting a Foreign Object in an Inductive Wireless Power Transfer System via Coupling Coefficient Measurement
Apparatus, System, and Method for Back-Channel Communication in an Inductive Wireless Power Transfer System
Apparatus, System, and Method for Detecting a Foreign Object in an Inductive Wireless Power Transfer System Based on Input Power
Timing Controllers Having Partitioned Pipelined Delay Chains Therein
Patent:
8,943,242 →
Application:
13/436,324 →
Apparatuses and System Having Separate Power Control and Timing Control of a Power Control System and Related Method
Apparatuses and System and Method for Auto-Configuration of a Power Control System
Apparatuses and Methods for Bitstream Bitstuffing
Application:
13/454,669 →
Publication:
US 2013/0279597
Apparatuses and Methods for Estimating Bitstream Bit Counts
Temperature Detection Method and Device with Improved Accuracy and Conversion Time
Linearizing a Power Amplifier
Ofdm Signal Processing in a Base Transceiver System
Power Management in an Electronic System Through Reducing Energy Usage of a Battery and/or Controlling an Output Power of an Amplifier Thereof
Transport Stream Multiplexers and Methods for Providing Packets on a Transport Stream
Method and Apparatus for Reducing Crowbar Current and Controlling Slew Rate
Patent:
8,723,573 →
Application:
13/528,387 →
Multiple Time Domain Synchronizer Circuits
Patent:
8,826,057 →
Application:
13/538,643 →
Mems-Based Frequency Synthesizers Having Variable Bandwidth Temperature Compensation
Patent:
8,604,848 →
Application:
13/538,719 →
Mems-Based Frequency Synthesizers with Enhanced Temperature Compensation
Patent:
8,575,981 →
Application:
13/538,759 →
Hybrid-Coding for Improving Transient Switch Response in a Multi-Cell Programmable Apparatus
Multi-Bit Cell Attenuator
Simultaneous Accommodation of a Low Power Signal and an Interfering Signal in a Radio Frequency (Rf) Receiver
Method and Apparatus for Efficient Baseband Unit Processing in a Communication System
Patent:
9,369,149 →
Application:
13/609,127 →
Method and Apparatus for Efficient Radio Unit Processing in a Communication System
Patent:
9,215,296 →
Application:
13/609,195 →
Apparatuses and Methods for Optimizing Rate-Distortion of Syntax Elements
Automatic Gain Control with Programmable Attack and Decay Times
Patent:
8,626,098 →
Application:
13/629,633 →
Microelectromechanical-Based Oscillators Having Adjustable Gain Amplifiers Therein That Support Q-Factor Control
Patent:
8,803,622 →
Application:
13/629,732 →
Current Mode Logic Circuits with Automatic Sink Current Adjustment
Patent:
8,847,628 →
Application:
13/631,933 →
Methods and Apparatuses for Adaptively Filtering Video Signals
Methods and Apparatuses for Providing an Adaptive Reduced Resolution Update Mode
Application:
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Publication:
US 2013/0188686
Clock Distribution Systems for Low Power Applications
Patent:
8,854,086 →
Application:
13/795,828 →
Methods of Packet-Based Synchronization in Non-Stationary Network Environments
Patent:
9,236,967 →
Application:
13/799,086 →
Apparatuses and Related Methods for Modulating Power of a Wireless Power Receiver
Clock Generation Circuits Using Jitter Attenuation Control Circuits with Dynamic Range Shifting
Patent:
9,065,459 →
Application:
13/829,202 →
Apparatuses and Related Methods for Charging Control of a Switching Voltage Regulator
Apparatuses and Methods for Providing Quantized Coefficients for Video Encoding
Microelectromechanical Resonators Having Offset [100] and [110] Crystal Orientations
Patent:
9,090,451 →
Application:
13/837,854 →
Packaged Mems-Based Oscillator Circuits That Support Frequency Margining and Methods of Operating Same
Patent:
9,000,853 →
Application:
13/849,999 →
Low Noise Variable Gain Amplifier Utilizing Variable Feedback Techniques with Constant Input/Output Impedance
Apparatuses, Methods, and Content Distribution System for Transcoding Bitstreams Using First and Second Transcoders
Methods of Forming Micro-Electromechanical Resonators Having Passive Temperature Compensation Regions Therein
Patent:
8,785,229 →
Application:
13/898,999 →
Reducing Charge Imbalance in a Charge Pump of a Phase Locked Loop (Pll) Through Maintaining an Output Node Thereof at a Same Voltage as a Bypass Node Thereof
Patent:
8,860,481 →
Application:
13/905,144 →
Adaptive Reference Voltage Generators That Support High Speed Signal Detection
Patent:
8,754,673 →
Application:
13/936,900 →
Multimode Wireless Power Receivers and Related Methods
Method and Apparatus for Efficient Data Compression in a Communication System
Patent:
9,203,933 →
Application:
14/012,944 →
Self-Adaptive Multi-Modulus Dividers Containing DIV2/3 Cells Therein
Patent:
9,118,333 →
Application:
14/013,599 →
High Frequency Precision Oscillators Having Stable Temperature Characteristics
Patent:
8,981,856 →
Application:
14/015,837 →
Apparatuses and Methods for Adjusting Coefficients Using Dead Zones
High Speed, Low Power, Isolated Multiplexer
High Speed, Low Power, Isolated Buffer
Method and Apparatus Utilizing Packet Segment Compression Parameters for Compression in a Communication System
Patent:
9,553,954 →
Application:
14/043,765 →
Multimode Wireless Power Transmitters and Related Methods
Application:
14/046,628 →
Publication:
US 2015/0097438
Method and Apparatus for Context Based Data Compression in a Communication System
Patent:
9,398,489 →
Application:
14/050,045 →
Method and Apparatus for Providing Near-Zero Jitter Real-Time Compression in a Communication System
Patent:
8,989,257 →
Application:
14/050,130 →
Method and Apparatus for Controlling Error and Identifying Bursts in a Data Compression System
Patent:
9,485,688 →
Application:
14/050,210 →
Wireless Power Transmitter Having Low Noise and High Efficiency, and Related Methods
Transmission of Multiprotocol Data in a Distributed Antenna System
Apparatuses and Methods for Over-Current Protection of Dc-Dc Voltage Converters
Apparatuses and Methods for Optimizing Rate-Distortion Costs in Video Encoding
Methods and Apparatuses for a Unified Compression Framework of Baseband Signals
Half-Integer Frequency Dividers That Support 50% Duty Cycle Signal Generation
Patent:
9,270,280 →
Application:
14/136,012 →
Packaged Integrated Circuits Having High-Q Inductors Therein and Methods of Forming Same
Patent:
9,397,151 →
Application:
14/136,040 →
Methods and Apparatuses for Content-Adaptive Quantization Parameter Modulation to Improve Video Quality in Lossy Video Coding
Application:
14/161,930 →
Publication:
US 2015/0208069
Monolithic Clock Generator and Timing/Frequency Reference
Apparatuses and Related Methods for Communication with a Wireless Power Receiver
Protection for Analog to Digital Converters
Process Compensated Delay
Patent:
9,264,027 →
Application:
14/190,890 →
Methods of Performing Time-of-Day Synchronization in Packet Processing Networks
Patent:
9,444,566 →
Application:
14/200,619 →
Digital Extraction and Correction of the Linearity of a Residue Amplifier in a Pipeline Adc
Systems and Methods for Estimation of Offset and Gain Errors in a Time-Interleaved Analog-to-Digital Converter
Dual-Coupled Phase-Locked Loops for Clock and Packet-Based Synchronization
Patent:
9,369,270 →
Application:
14/212,598 →
Methods and Apparatuses for Slew Rate Enhancement of Amplifiers
Apparatuses and Methods for Over-Temperature Protection of Energy Storage Devices
Extending Beamforming Capability of a Coupled Voltage Controlled Oscillator (Vco) Array During Local Oscillator (Lo) Signal Generation Through Frequency Multiplication
Extending Beamforming Capability of a Coupled Voltage Controlled Oscillator (Vco) Array During Local Oscillator (Lo) Signal Generation Through a Circular Configuration Thereof
Phase Shift Based Improved Reference Input Frequency Signal Injection into a Coupled Voltage Controlled Oscillator (Vco) Array During Local Oscillator (Lo) Signal Generation to Reduce a Phase-Steering Requirement During Beamforming
EXTENDING BEAMFORMING CAPABILITY OF A COUPLED VOLTAGE CONTROLLED OSCILLATOR (VCO) ARRAY DURING LOCAL OSCILLATOR (LO) SIGNAL GENERATION THROUGH ACCOMMODATING DIFFERENTIAL COUPLING BETWEEN VCOs THEREOF
Extending Beamforming Capability of a Coupled Voltage Controlled Oscillator (Vco) Array During Local Oscillator (Lo) Signal Generation Through Fine Control of a Tunable Frequency of a Tank Circuit of a Vco Thereof
Adaptive Transmit Array for Beam-Steering
Automatic High-Resolution Adaptive Beam-Steering
Constant Impedance Switch
Methods and Apparatuses for Edge Preserving and/or Edge Enhancing Spatial Filter
Methods and Apparatuses for Stripe-Based Temporal and Spatial Video Processing
Application:
14/326,211 →
Publication:
US 2016/0014417
Long-Distance Rapidio Packet Delivery
Digital Filter for Phase-Locked Loop Integrated Circuits
Patent:
9,236,871 →
Application:
14/460,653 →
Low Power Driver with Programmable Output Impedance
Initiating Operation of a Timing Device Using a Read Only Memory (Rom) or a One Time Programmable Non Volatile Memory (Otp Nvm)
Apparatuses and Related Methods for Generating Wireless Status Indications for a Wireless Power Transfer System
Apparatuses and Methods for Filtering Noise from a Video Signal
Methods and Apparatuses for Power Control During Backscatter Modulation in Wireless Power Receivers
Suppression of Audible Harmonics in Wireless Power Receivers
Apparatuses and Related Methods for Detecting Coil Alignment with a Wireless Power Receiver
Method and Apparatus for Operating of a PCIe Retimer over Optical Cable
Patent:
10,146,722 →
Application:
14/514,736 →
Method and Apparatus for Congestion and Fault Management with Time-to-Live
Patent:
9,203,769 →
Application:
14/530,582 →
Crystal-Less Jitter Attenuator
Patent:
9,553,570 →
Application:
14/566,571 →
Fractional Divider Based Phase Locked Loops with Digital Noise Cancellation
Patent:
9,236,873 →
Application:
14/573,146 →
Self-Calibrating Fractional Divider Circuits
Patent:
9,479,177 →
Application:
14/575,212 →
Overvoltage Protection Circuits and Methods of Operating Same
Patent:
9,793,708 →
Application:
14/576,288 →
Integrated Circuit Device Substrates Having Packaged Crystal Resonators Thereon
Patent:
9,306,537 →
Application:
14/586,508 →
Integrated Circuit Device Substrates Having Packaged Inductors Thereon
Patent:
9,478,599 →
Application:
14/586,525 →
Crystal Oscillator Fabrication Methods Using Dual-Deposition of Mounting Cement and Dual-Curing Techniques
Patent:
9,445,536 →
Application:
14/586,534 →
Apparatuses and Methods for Efficient Random Noise Encoding
Application:
14/592,539 →
Publication:
US 2016/0205398
Apparatus, System, and Method for Back-Channel Communication in an Inductive Wireless Power Transfer System
Apparatuses and Related Methods for Detecting Magnetic Flux Field Characteristics with a Wireless Power Receiver
Apparatuses and Related Methods for Detecting Magnetic Flux Field Characteristics with a Wireless Power Transmitter
Fractional Reference-Injection Pll
Patent:
9,369,139 →
Application:
14/622,851 →
Output Driver Having Output Impedance Adaptable to Supply Voltage and Method of Use
Patent:
9,419,588 →
Application:
14/628,215 →
System and Method for Voltage Regulation of One-Time-Programmable (Otp) Memory Programming Voltage
Patent:
9,336,896 →
Application:
14/666,226 →
Apparatuses and Wireless Power Transmitters Having Multiple Transmit Coils and Related Method
Apparatuses and Related Methods for a Wireless Power Receiver Using Coupled Inductors
Wireless Power System
Reduced VSWR Switching
Methods and Apparatus for IO, Processing and Memory Bandwidth Optimization for Analytics Systems
Application:
14/673,724 →
Publication:
US 2016/0292115
Methods and Apparatus for Efficient Network Analytics and Computing Card
Application:
14/673,818 →
Publication:
US 2016/0292117
Method and Apparatus for Using Tester Channel as Device Power Supply
Patent:
9,500,707 →
Application:
14/674,330 →
Process Compensated Delay
Patent:
10,110,209 →
Application:
14/675,369 →
Low Latency Interconnect Integrated Event Handling
Patent:
9,921,891 →
Application:
14/675,498 →
Enhanced Data Buffer and Intelligent NV Controller for Simultaneous DRAM and Flash Memory Access
Patent:
10,394,460 →
Application:
14/675,591 →
High Efficiency Wireless Power System
Controlling Operation of a Timing Device Using an Otp Nvm to Store Timing Device Configurations in a Ram
Patent:
9,455,045 →
Application:
14/691,472 →
Low Voltage Differential Signaling (Lvds) Driver with Differential Output Signal Amplitude Regulation
Patent:
9,407,268 →
Application:
14/700,034 →
System and Method for Wireless Power Transfer Using a Two Half-Bridge to One Full-Bridge Switchover
Method and Apparatus for Parallel Decoding
System and Method for Synchronous Rectification with Enhanced Detection of Small Currents
Method for Time-Dependent Visual Quality Encoding for Broadcast Services
Methods and Apparatuses for Filtering of Ringing Artifacts Post Decoding
Apparatuses and Methods for Performing Information Extraction and Insertion on Bitstreams
System and Method for Wireless Power Transfer Using Automatic Power Supply Selection
Method and Apparatus for Fast Frequency Acquisition in PLL System
Patent:
9,362,924 →
Application:
14/794,770 →
Low-Spurious Fractional N-Frequency Divider and Method of Use
Patent:
9,362,928 →
Application:
14/794,782 →
Transport Stream Multiplexers and Methods for Providing Packets on a Transport Stream
Timing Device Having Multi-Purpose Pin with Proactive Function
Patent:
9,954,516 →
Application:
14/830,698 →
High-Speed Programmable Frequency Divider with 50% Output Duty Cycle
Patent:
9,590,637 →
Application:
14/839,817 →
Integrated Circuit Devices Having Oscillator Circuits Therein That Support Fixed Frequency Generation Over Process-Voltage-Temperature (Pvt) Variations
Patent:
9,503,059 →
Application:
14/871,319 →
Packaged Oscillators with Built-in Self-Test Circuits That Support Resonator Testing with Reduced Pin Count
Patent:
9,791,503 →
Application:
14/871,411 →
Wireless Power Transmitter
INTEGRATED CIRCUITS HAVING MULTIPLE DIGITALLY-CONTROLLED OSCILLATORS (DCOs) THEREIN THAT ARE SLAVED TO THE SAME LOOP FILTER
Patent:
9,490,828 →
Application:
14/884,324 →
Integrated Circuits Having Low Power, Low Interference and Programmable Delay Generators Therein and Methods of Operating Same
Patent:
9,438,252 →
Application:
14/887,663 →
Method and Apparatus for Current Steering in High Sensitivity, High Linearity and Large Dynamic Range High Speed Trans-Impedance Amplifiers
Receiver Equalization Circuit with Cross Coupled Transistors and/or Rc Impedance
Patent:
9,583,175 →
Application:
14/956,870 →
Asymmetrical Emphasis in a Memory Data Bus Driver
System and Method for Deskewing Output Clock Signals
Patent:
9,614,508 →
Application:
14/958,701 →
Design for Testability/Manufacturing Method to Adjust Output Skew Timing
Patent:
9,640,278 →
Application:
14/964,953 →
Multi-Stage Frequency Dividers Having Duty Cycle Correction Circuits Therein
Patent:
9,543,960 →
Application:
14/966,913 →
System and Method for Providing Hermetically Sealed Packages with Consistent Vacuum Cavity
Application:
14/967,007 →
Publication:
US 2017/0166442
System and Method for Improving Dicing Quality for Bonded Wafer Pairs
Application:
14/967,050 →
Publication:
US 2017/0170159
Methods and Apparatus for Transmitting Data Over a Clock Signal
Patent:
9,628,255 →
Application:
14/975,226 →
Methods and Apparatus for Synchronizing Operations Using Separate Asynchronous Signals
Patent:
9,479,182 →
Application:
14/975,388 →
Wireless Power Receiver with Magnetic Data Transaction Capability
Monolithic Composite Resonator Devices with Reduced Sensitivity to Acceleration and Vibration
Patent:
9,431,955 →
Application:
14/985,689 →
Methods of Estimating Frequency Skew in Networks Using Timestamped Packets
Patent:
10,374,786 →
Application:
14/992,486 →
Single-Ended Memory Signal Equalization at Power Up
Patent:
9,589,626 →
Application:
14/993,271 →
Signal Driver Slew Rate Control
Power Management in an Electronic System Through Reducing Energy Usage of a Battery and/or Controlling an Output Power of an Amplifier Thereof
Power Management in an Electronic System Through Reducing Energy Usage of a Battery and/or Controlling an Output Power of an Amplifier Thereof
Phase Locked Loop (Pll) Timing Device Evaluation System and Method for Evaluating Pll Timing Devices
Patent:
9,852,039 →
Application:
15/015,094 →
Adaptive High-Speed Current-Steering Logic (Hcsl) Drivers
Patent:
9,838,016 →
Application:
15/050,646 →
Methods and Apparatuses for a Unified Compression Framework of Baseband Signals
Memory Includes Transmitter for Data Synchronization Transmission After a Mode Switch and Method Thereof
Patent:
9,552,870 →
Application:
15/059,555 →
Asymmetric on-State Resistance Driver Optimized for Multi-Drop DDR4
Buffer with Programmable Input/Output Phase Relationship
Patent:
9,859,901 →
Application:
15/064,369 →
Adaptive Resonant Topology Application in Wearable Devices
Methods and Systems for Analog-to-Digital Conversion (Adc) Using an Ultra Small Capacitor Array with Full Range and Sub-Range Modes
Patent:
9,553,602 →
Application:
15/076,327 →
Single-Ended Signal Equalization with a Programmable 1-Tap Decision Feedback Equalizer
Patent:
9,542,991 →
Application:
15/079,370 →
Programmable Low Power High-Speed Current Steering Logic (Lphcsl) Driver and Method of Use
Patent:
9,692,394 →
Application:
15/081,723 →
Integrated Low Voltage Differential Signaling (LVDS) and High-Speed Current Steering Logic (HCSL) Circuit and Method of Use
Patent:
9,698,787 →
Application:
15/083,068 →
Dual Mode Clock Using a Common Resonator and Associated Method of Use
Patent:
9,581,973 →
Application:
15/083,831 →
Bulk Acoustic Wave Resonator Based Fractional Frequency Synthesizer and Method of Use
Patent:
9,954,541 →
Application:
15/084,067 →
Arbitrary Delay Buffer
System and Method for Wireless Power Transfer Using Over-Voltage Protection
Flexible Point-to-Point Memory Topology
Single-Ended Signal Slicer with a Wide Input Voltage Range
Patent:
9,583,155 →
Application:
15/093,876 →
Multi-Bit Cell Attenuator
GAAS/SIGE-BICMOS-Based Transceiver System-in-Package for E-Band Frequency Applications
Calibration Method and Apparatus for Phase Locked Loop Circuit
Patent:
9,654,121 →
Application:
15/169,997 →
On-Die Verification of Resistor Fabricated in Cmos Process
Fractional Divider Using a Calibrated Digital-to-Time Converter
Patent:
9,678,481 →
Application:
15/185,378 →
Frequency Synthesizer with Microcode Control
Patent:
9,847,869 →
Application:
15/210,204 →
Fast-Response Hybrid Lock Detector
Patent:
9,831,882 →
Application:
15/226,286 →
Scalable Coherent Apparatus and Method
Patent:
10,235,295 →
Application:
15/247,854 →
Adjustable Termination Circuit for High Speed Laser Driver
Hierarchical Caching and Analytics
Dual Use Bootstrap Driver
Multimode Wireless Power Receiver Circuit
Frequency Divider with Selectable Frequency and Duty Cycle
Pulse Width Modulation (PWM) to Align Clocks Across Multiple Separated Cards Within a Communication System
Patent:
10,075,284 →
Application:
15/364,602 →
Inferring Sampled Data in Decision Feedback Equalizer at Restart of Forwarded Clock in Memory System
Patent:
9,860,088 →
Application:
15/367,586 →
Compensation of Deterministic Crosstalk in Memory System
Patent:
9,865,315 →
Application:
15/367,672 →
Command Sequence Response in a Memory Data Buffer
Patent:
10,198,200 →
Application:
15/367,742 →
Nullifying Incorrect Sampled Data Contribution in Decision Feedback Equalizer at Restart of Forwarded Clock in Memory System
Patent:
9,865,328 →
Application:
15/367,968 →
Synchronization of Data Transmission with a Clock Signal After a Memory Mode Switch
Memory Channel Selection Control
Gas Sensor
Application:
15/405,089 →
Publication:
US 2018/0196022
Multimode Wireless Power Transmitters and Related Methods
Application:
15/405,861 →
Publication:
US 2017/0126071
Frequency Synthesizer with Tunable Accuracy
Resynchronization of a Clock Associated with Each Data Bit in a Double Data Rate Memory System
High Frequency Wireless Power Rectifier Startup Circuit Design
Patent:
9,899,908 →
Application:
15/440,463 →
Pulse Width Modulation (PWM) to Align Clocks Across Multiple Separated Cards Within a Communication System
Application:
62/281,332 →
Method and Apparatus for Flexible Coherent and Scale-out Computing Architecture
Application:
62/298,341 →
Related Assignments
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Corrective Assignment to Correct the Receiving Party's Name Previously Recorded at Reel: 016702 Frame: 0052. Assignor(S) Hereby Confirms the Assignment.
Oct 23, 2014
From: STREAM MACHINE, INC.
To: MAGNUM SEMICONDUCTOR, INC.
Reel/Frame 034037/0253 →
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Oct 31, 2014
From: MAGNUM SEMICONDUCTOR, INC.
To: CAPITAL IP INVESTMENT PARTNERS LLC, AS ADMINISTRATIVE AGENT
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Apr 6, 2016
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Amended and Restated Intellectual Property Security Agreement
Apr 6, 2016
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To: SILICON VALLEY BANK
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Release of Security Interest
Apr 15, 2016
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To: MAGNUM SEMICONDUCTOR, INC.
Reel/Frame 038440/0565 →
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Apr 5, 2017
From: SILICON VALLEY BANK
To: ENDWAVE CORPORATION
Reel/Frame 042166/0194 →
Release of Security Interest
Apr 5, 2017
From: SILICON VALLEY BANK
To: MAGNUM SEMICONDUCTOR, INC.
Reel/Frame 042166/0405 →
Security Agreement
Apr 5, 2017
From: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; MAGNUM SEMICONDUCTOR, INC.; ENDWAVE CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 042166/0431 →
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Aug 4, 2017
From: MAGNUM SEMICONDUCTOR, INC.
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 043207/0637 →
Assignment of Assignor's Interest
Jan 15, 2024
From: MASOR, LAURA L.
To: BALL HORTICULTURAL COMPANY
Reel/Frame 066121/0147 →