Timing controllers having partitioned pipelined delay chains therein

1. A timing controller, comprising:

a pipelined delay chain configured to process commands and control signals associated with the commands between a first device and a plurality of second devices having different timing requirements, said pipelined delay chain comprising a cascaded arrangement of a primary delay chain, at least one secondary delay chain and a plurality of control signal sequence generators responsive to signals generated by the at least one secondary delay chain, said primary delay chain comprising a plurality of serially-linked registers configured to support a pipelining of the commands and a primary delay stack configured to support operations to push and pop the control signals associated with the commands to and from the primary data stack;

wherein said primary delay chain is configured to pop first control signals associated with a first command from the primary data stack in response to passing the first command through the primary delay chain;

wherein the first control signals include information identifying the first command and timing related information associated with a first of the plurality of second devices; and

wherein the at least one secondary delay chain is configured to independently delay signals associated with at least a first clock and at least first data based on timing parameters associated with the first command and the timing related information associated with the first of the plurality of second devices.

2. The timing controller of claim 1 , wherein the primary delay chain is configured to provide a programmable delay.

3. The timing controller of claim 2 , wherein the at least one secondary delay chain is configured to provide a programmable delay.

4. The timing controller of claim 3 , wherein each of the plurality of control signal sequence generators is configured to provide a programmable delay.

5. The timing controller of claim 1 , wherein the primary data stack is a first-in first-out (FIFO) buffer configured to pop control signals associated with a first command from the primary data stack in-sync with an exiting of the first command from the primary delay chain.

6. The timing controller of claim 1 , wherein the plurality of control signal sequence generators generate a plurality of pulses having unique timing and duration.

7. The timing controller of claim 6 , wherein the at least one secondary delay chain comprises at least one secondary data stack configured to receive control signals from the primary data stack.

8. A timing controller, comprising:

a pipelined delay chain configured to process commands and control signals associated with the commands between a first device and a plurality of second devices having different timing requirements, said pipelined delay chain comprising a cascaded arrangement of a primary delay chain and at least one secondary delay chain, said primary delay chain comprising a plurality of serially-linked registers configured to support a pipelining of the commands and a stack configured to support operations to push and pop the control signals associated with the commands to and from the stack;

wherein said primary delay chain is configured to pop first control signals associated with a first command from the stack in response to passing the first command through the primary delay chain;

wherein the first control signals include information identifying the first command and timing related information associated with a first of the plurality of second devices; and

wherein the at least one secondary delay chain is configured to independently delay signals associated with at least a first clock and at least first data based on timing parameters associated with the first command and the timing related information associated with the first of the plurality of second devices.

9. The timing controller of claim 8 , wherein the primary delay chain is configured to provide a programmable delay.

10. The timing controller of claim 9 , wherein the at least one secondary delay chain is configured to provide a programmable delay.

11. The timing controller of claim 8 , wherein the stack is a first-in first-out (FIFO) buffer configured to pop control signals associated with a first command from the stack in-sync with an exiting of the first command from the primary delay chain.

12. A timing controller, comprising:

a pipelined delay chain configured to process commands and control signals associated with writing and reading data to and from a plurality of memory devices, said pipelined delay chain comprising a cascaded arrangement of a primary delay chain, at least one secondary delay chain and a plurality of control signal sequence generators responsive to signals generated by the at least one secondary delay chain, said primary delay chain comprising a plurality of serially-linked registers configured to support a pipeline of read/write commands and a stack configured to support operations to push and pop the control signals associated with the read/write commands to and from the stack;

wherein said primary delay chain is configured to pop first control signals associated with a first read/write command from the stack in response to passing of the first read/write command through the primary delay chain;

wherein the first control signals include first command type and first rank information associated with a first of the memory devices; and

wherein the at least one secondary delay chain is configured to independently delay at least four timing signals associated with an input clock, input data, an output clock and output data based on timing parameters associated with the first command type and first rank information.