IP Library Granted Patent US 8,981,856
Granted Patent B1
US 8,981,856 · App. 14/015,837 · Granted Mar 17, 2015

High frequency precision oscillators having stable temperature characteristics

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Quick Facts
Patent No.
US 8,981,856
App. No.
14/015,837
Granted
Mar 17, 2015
Kind
B1
Abstract

An oscillator circuit includes an adjustable frequency oscillator configured to free-run at a first frequency below a desired second target frequency. This adjustable frequency oscillator is configured to modulate a frequency of its periodic output signal upwards from the first frequency to the second frequency in response to a feedback bias current. A divider is also provided, which is configured to convert the periodic output signal to a reduced-frequency control signal. This reduced-frequency control signal is provided to a frequency-to-current (F2C) converter, which is configured to drive the adjustable frequency oscillator with the feedback bias current (e.g., pull-down current) in response to the reduced-frequency control signal.

Claims (19)

1. An oscillator circuit, comprising:

an adjustable frequency oscillator configured to free-run at a first frequency below a desired second frequency, said adjustable frequency oscillator configured to modulate a frequency of its periodic output signal upwards from the first frequency to the second frequency in response to a feedback bias current;

a divider configured to convert the periodic output signal to a reduced-frequency control signal; and

a frequency-to-current converter configured to drive the adjustable frequency oscillator with the feedback bias current in response to the reduced-frequency control signal, said frequency-to-current converter comprising a cascaded arrangement of a frequency-to-voltage converter and an error amplifier, said frequency-to-voltage converter comprising a ramp generator and said error amplifier comprising a sampling amplifier.

2. The oscillator circuit of claim 1 , wherein the frequency-to-voltage converter is responsive to a bandgap reference voltage.

3. The oscillator circuit of claim 1 , wherein the frequency-to-voltage converter is configured to perform a frequency-to-voltage conversion at the frequency of the reduced-frequency control signal.

4. The oscillator circuit of claim 3 , wherein said divider is configured to perform a divide-by-2 N operation, where N is an integer greater than two.

5. The oscillator circuit of claim 1 , wherein the frequency-to-voltage converter comprises a frequency measurement decoder electrically coupled to a plurality of stages within said divider.

6. The oscillator circuit of claim 1 , further comprising a bias signal generator configured to generate a first bias voltage, which is provided to said frequency-to-current converter.

7. The oscillator circuit of claim 6 , wherein said frequency-to-current converter is configured to generate the feedback bias current at a first output thereof; and wherein said adjustable frequency oscillator and said bias signal generator are electrically coupled to the first output of said frequency-to-current converter.

8. The oscillator circuit of claim 1 , wherein said adjustable frequency oscillator is a dual-ramp oscillator.

9. An oscillator circuit, comprising:

an oscillator configured to modulate a frequency of its periodic output signal in response to a feedback bias current;

a divider configured to convert the periodic output signal to a reduced-frequency control signal; and

a frequency-to-current converter configured to drive said oscillator with the feedback bias current in response to the reduced-frequency control signal, said frequency-to-current converter comprising a cascaded arrangement of a frequency-to-voltage converter, which comprises a ramp generator, and a sampling error amplifier.

10. The oscillator circuit of claim 9 , wherein the frequency-to-voltage converter comprises a frequency measurement decoder electrically coupled to a plurality of stages within said divider.

11. The oscillator circuit of claim 9 , further comprising a bias signal generator configured to generate a first bias voltage, which is provided to said frequency-to-current converter.

12. The oscillator circuit of claim 11 , wherein said frequency-to-current converter is configured to generate the feedback bias current at a first output thereof; and wherein said adjustable frequency oscillator and said bias signal generator are electrically coupled to the first output of said frequency-to-current converter.

13. The oscillator circuit of claim 9 , wherein said oscillator is a dual-ramp oscillator.

Assignments (3)
RELEASE OF SECURITY INTEREST Recorded Mar 29, 2019
From: JPMORGAN CHASE BANK, N.A.
To: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; CHIPX, INCORPORATED; ENDWAVE CORPORATION; MAGNUM SEMICONDUCTOR, INC.
Reel/Frame 048746/0001 →
SECURITY AGREEMENT Recorded Apr 5, 2017
From: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; MAGNUM SEMICONDUCTOR, INC.; ENDWAVE CORPORATION; CHIPX, INCORPORATED
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 042166/0431 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 4, 2013
From: NEWLIN, TREVOR
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 031350/0166 →