IP Library Granted Patent US 7,940,762
Granted Patent B2
US 7,940,762 · App. 12/051,720 · Granted May 10, 2011

Content driven packet switch

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Quick Facts
Patent No.
US 7,940,762
App. No.
12/051,720
Granted
May 10, 2011
Kind
B2
Abstract

A packet switch routes data packets based on both packet headers and data payloads in the data packets. The packet switch receives data packets, identifies a destination port of the packet switch for each data packet based on a packet header of the data packet, and routes the data packet to the destination port. Additionally, the packet switch selects data packets among the data packets received by the packet switch based on the data payloads of the received data packets, identifies a trace port of the packet switch for each selected data packet, and routes the selected data packet to the trace port.

Claims (37)

1. A packet switch, comprising:

a switch fabric;

a first port coupled to the switch fabric and comprising a first packet engine configured to receive a first data packet including a packet header and a data payload;

a second port coupled to the switch fabric, the first packet engine further configured to identify the second port based on the packet header of the first data packet, the switch fabric configured to route the first data packet to the second port, the second port configured to output the first data packet from the packet switch; and

a third port coupled to the switch fabric, the first packet engine further configured to select the first data packet for routing to a trace port based on the data payload of the first data packet and identify the third port as the trace port based on both the packet header and the data payload of the first data packet, the switch fabric further configured to route the first data packet to the trace port for analysis of packet communication through the packet switch.

2. The packet switch of claim 1 , wherein the first packet engine is further configured to select the first data packet based on the data payload of the first data packet by comparing the first data packet with a data pattern.

3. The packet switch of claim 2 , wherein the first packet engine is further configured to compare the first data packet with the data pattern by masking the data packet with a data mask to generate a result and comparing the result with the data pattern.

4. The packet switch of claim 1 , wherein the trace port comprises a second packet engine configured to generate a second data packet indicating a start trace event occurring in the packet switch and generate a third data packet indicating a stop trace event occurring in the packet switch, and wherein the trace port is configured to output the second data packet and the third data packet from the packet switch.

5. The packet switch of claim 4 , wherein each of the second data packet and the third data packet conforms to a serial RapidIO format and comprises a port write command.

6. The packet switch of claim 1 , wherein the trace port comprises a second packet engine including a trace buffer configured to store packets received by the trace port.

7. The packet switch of claim 6 , wherein the first packet engine comprises comparators each configured to generate a result by comparing the first data packet with a data pattern associated with the comparator, and the first packet engine is further configured to select the first data packet based on the results generated by the comparators.

8. A method comprising:

receiving a first data packet including a packet header and a data payload at a first port of a packet switch;

identifying a second port of the packet switch based on the packet header of the first data packet;

routing the first data packet to the second port of the packet switch;

outputting the first data packet from the packet switch at the second port;

selecting the first data packet for routing to a trace port based on the data payload of the first data packet;

identifying a third port of the packet switch as the trace port based on both the packet header and the data payload of the first data packet; and

routing the first data packet to the trace port of the packet switch for analysis of packet communication through the packet switch.

9. The method of claim 8 , wherein selecting the first data packet for routing to the trace port based on the data payload of the first data packet comprises comparing the first data packet with at least one data pattern.

10. The method of claim 9 , wherein comparing the first data packet with the at least one data pattern comprises:

masking the data packet with a data mask to generate a result; and

comparing the result with the at least one data pattern.

11. The method of claim 9 , wherein receiving the first data packet comprises receiving the first data packet as a bit stream, and wherein comparing the first data packet with the data pattern comprises performing a bit-by-bit comparison of a portion of the first data packet with the data pattern before receiving the entire first data packet.

12. The method of claim 8 , further comprising:

generating a second data packet indicating a start trace event occurring in the packet switch;

outputting the second data packet from the packet switch;

generating a third data packet indicating a stop trace event occurring in the packet switch; and

outputting the third data packet from the packet switch.

13. A packet switch, comprising:

a switch fabric;

a first port coupled to the switch fabric and comprising a first packet engine configured to receive a first data packet including a packet header and a data payload;

a second port coupled to the switch fabric, the first packet engine further configured to identify the second port based on the packet header of the first data packet, the switch fabric configured to route the first data packet to the second port, the second port configured to output the first data packet from the packet switch;

a third port coupled to the switch fabric, the first packet engine further configured to select the first data packet for routing to a trace port based on the data payload of the first data packet and identify the third port as the trace port based on the packet header and the data payload of the first data packet, the switch fabric further configured to route the first data packet to the trace port for analysis of packet communication through the packet switch; and

wherein the first packet engine comprises comparators, each comparator configured to generate a result by comparing the first data packet with a data pattern associated with the comparator, and the first packet engine is further configured to select the first data packet for routing to a trace port based on the results generated by the comparators.

14. The packet switch of claim 13 , wherein the trace port comprises a second packet engine including a trace buffer configured to store packets received by the trace port.

15. The packet switch of claim 13 , wherein the trace port comprises a second packet engine configured to generate a second data packet indicating a start trace event occurring in the packet switch and generate a third data packet indicating a stop trace event occurring in the packet switch, and wherein the trace port is configured to output the second data packet and the third data packet from the packet switch.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2025
From: RENESAS ELECTRONICS AMERICA INC.
To: AXIRO SEMICONDUCTOR INC.
Reel/Frame 070864/0142 →
MERGER Recorded Apr 15, 2025
From: INTEGRATED DEVICE TECHNOLOGY, INC.
To: RENESAS ELECTRONICS AMERICA INC.
Reel/Frame 070851/0391 →
RELEASE OF SECURITY INTEREST Recorded Mar 29, 2019
From: JPMORGAN CHASE BANK, N.A.
To: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; CHIPX, INCORPORATED; ENDWAVE CORPORATION; MAGNUM SEMICONDUCTOR, INC.
Reel/Frame 048746/0001 →
SECURITY AGREEMENT Recorded Apr 5, 2017
From: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; MAGNUM SEMICONDUCTOR, INC.; ENDWAVE CORPORATION; CHIPX, INCORPORATED
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 042166/0431 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 19, 2008
From: DARNELL, BRIAN SCOTT; PREYER, JUSTIN
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 020675/0967 →