Patent Assignment
Reel/Frame 070864/0142
Assignment of Assignor's Interest
Recorded: 2025-04-16
Pages: 15
Assignor
RENESAS ELECTRONICS AMERICA INC.
Executed: 2025-04-03
Assignee
AXIRO SEMICONDUCTOR INC.
10180 TELESIS COURT, SUITE 320, SAN DIEGO, CALIFORNIA, 92121
Covered Properties
(105)
Gain Variation Compensation Using Temperature Attenuator
Integrated Power Amplifier with Bias Control and Harmonic Termination
Spurious Emissions Detection and Calibration Using Envelope Detector
Method of Manufacturing Semiconductor Device, Method of Manufacturing Semiconductor Module, and Semiconductor Device
Application:
18/470,781 →
Publication:
US US20250096183A1
Broadband Interstage Matching
Application:
18/390,967 →
Publication:
US US20250211171A1
Circuit for Correcting Amplitude Imbalance and Phase Imbalance
Method, Device and Apparatus for Biasing a Power Amplifier Operative Over Wide Supply Range
Application:
18/241,850 →
Publication:
US US20250080064A1
Three Stage Power Amplifier with Balanced Driver Stage
Application:
19/050,436 →
Radio Frequency Pre-Drivers with Input Over Voltage Protection
Application:
18/822,351 →
Publication:
US US20260066852A1
Three Stage Power Amplifier with Peak Output Match
Application:
18/742,112 →
Publication:
US US20250385643A1
Matched Feedback Amplifier with Improved Linearity
Low Noise Variable Gain Amplifier Utilizing Variable Feedback Techniques with Constant Input/Output Impedance
Low Noise Variable Gain Amplifier Utilizing Variable Feedback Techniques with Constant Input/Output Impedance
Hybrid-Coding for Improving Transient Switch Response in a Multi-Cell Programmable Apparatus
Multi-Bit Cell Attenuator
Multi-Bit Cell Attenuator
Constant Impedance Switch
Reduced VSWR Switching
Circuits and Systems for Wideband Quadrature Signal Generation
Simultaneous Accommodation of a Low Power Signal and an Interfering Signal in a Radio Frequency (Rf) Receiver
Transceiver Resonant Receive Switch
Patent:
10,312,961 →
Application:
15/841,692 →
Transceiver Resonant Receive Switch
Patent:
10,511,344 →
Application:
16/229,542 →
Rf Amplifier Linearity Enhancement with Dynamically Adjusted Variable Load
Method to Build Asymmetrical Transmit/Receive Switch with 90 Degrees Impedance Transformation Section
Method to Build Asymmetrical Transmit/Receive Switch with 90 Degrees Impedance Transformation Section
Patent:
10,063,274 →
Application:
15/825,736 →
Ultrafast and Precise Gain Control Step in Rf Amplifiers
Wideband Vector Modulator and Phase Shifter
Reduced Transistor Bridge Attenuator
90 Degree Differential Signal Layout Transition
Fast Memory Access Control for Phase and Gain
Fast Memory Access Control for Phase and Gain
Patent:
10,063,303 →
Application:
15/817,909 →
Hard-Wired Address for Phased Array Antenna Panels
Symmetrical Front-End Chip for Dual-Pole Antenna Array
Front-End Chip for Dual-Pole Antenna Array
Method to Improve Power Amplifier Output Return Loss and Back-Off Performance with Rc Feedback Network
Method to Improve Power Amplifier Output Return Loss and Back-Off Performance with Rc Feedback Network
Method to Improve Power Amplifier Output Return Loss and Back-Off Performance with Rc Feedback Network
Radio-Frequency Signal Shielding and Channel Isolation
Distributed Transceiver Signal Switching Circuit
Distributed Transceiver Signal Switching Circuit
Method to Build Fast Transmit-Receive Switching Architecture
Method for Separately Biasing Power Amplifier for Additional Power Control
Rf Switch with Digital Gate Threshold Voltage
High Power Silicon on Insulator Switch
Real-Time and Adaptive Radio-Frequency Power Protection
Real-Time and Adaptive Radio-Frequency Power Protection
Real-Time and Adaptive Radio-Frequency Power Protection
Linear-In-Db Log-Amp with Calibration for Power Detection
Patent:
10,763,913 →
Application:
16/372,698 →
Power Amplifier Bias Network Implementation for Improving Linearity for Wideband Modulated Signals
Transmit-Receive Switch with Integrated Power Detection
Patent:
10,536,186 →
Application:
16/354,650 →
Transmit-Receive Switch with Integrated Power Detection
Beam Forming Module Implementation for High Isolation and Low Noise Figure Systems
Patent:
10,720,985 →
Application:
16/354,791 →
Compact Balanced Radio Frequency Balun Facilitating Easy Integration
Design Principle and Techniques for Integrated Trx Switch
Minimizing Impedance Variation During Passive Phase Shifting
Sub-Micron Cmos High-Power Cascode Rf Power Amplifier
Power Amplifier Biasing Network Providing Gain Expansion
Sliding Window and DC Offset Correction Technique for Pulse Doppler Radar Systems
Dynamic Amplifier Supply in a Phased Antenna Array
Three-Way Combined Rf Power Amplifier Architecture
Time Slot Interchange Switch with Bit Error Rate Testing
Packet Processing Switch and Methods of Operation Thereof
Packet Processing Switch and Methods of Operation Thereof
Error Management System and Method for a Packet Switch
Patent:
7,747,904 →
Application:
11/383,121 →
System and Method of Constructing Data Packets in a Packet Switch
Patent:
7,817,652 →
Application:
11/383,150 →
System and Method for Arbitration in a Packet Switch
Patent:
7,684,431 →
Application:
11/407,321 →
Method and Structure to Support System Resource Access of a Serial Device Implementing a Lite-Weight Protocol
Hardware-Based Concurrent Direct Memory Access (DMA) Engines On Serial Rapid Input/Output SRIO Interface
Rapid Input/Output Doorbell Coalescing to Minimize Cpu Utilization and Reduce System Interrupt Latency
Multi-Bus Structure for Optimizing System Performance of a Serial Buffer
System and Method for Arbitration Using Availability Signals
Patent:
8,289,989 →
Application:
11/419,572 →
System and Method for Round Robin Arbitration
Patent:
7,706,387 →
Application:
11/421,415 →
Method To Support Flexible Data Transport On Serial Protocols
Protocol Translation in a Serial Buffer
Serial Buffer to Support Request Packets with Out of Order Response Packets
Multi-Function Queue to Support Data Offload, Protocol Translation and Pass-Through Fifo
Adaptive Interrupt on Serial Rapid Input/Output (Srio) Endpoint
Method to Support Lossless Real Time Data Sampling and Processing on Rapid I/O End-Point
Content Driven Packet Switch
Packet Switch with Port Route Tables
Patent:
8,040,888 →
Application:
11/958,313 →
Packet Latency Based Arbitration Technique for a Packet Switch
Patent:
8,014,288 →
Application:
12/266,377 →
Old Virtual Queues Technique for Routing Data Packets in a Packet Switch
Patent:
8,081,646 →
Application:
12/328,953 →
Power Reduction Technique for Buffered Crossbar Switch
Patent:
7,907,625 →
Application:
12/185,716 →
Packet Switch with Configurable Bandwidth Allocation Precision
Patent:
7,796,629 →
Application:
12/331,372 →
High Speed Switch With Data Converter Physical Ports And Processing Unit
High Speed Switch with Data Converter Physical Ports
A Method and System for Providing Fault Tolerance in a Network
Method and Apparatus for Dynamic Traffic Management with Packet Classification
Patent:
8,325,723 →
Application:
12/712,516 →
Method and Apparatus for Congestion and Fault Management with Time-to-Live
Patent:
8,902,765 →
Application:
12/712,560 →
Method and Apparatus for Congestion and Fault Management with Time-to-Live
Patent:
9,203,769 →
Application:
14/530,582 →
Method and Apparatus for Programmable Buffer with Dynamic Allocation to Optimize System Throughput with Deadlock Avoidance on Switches
Patent:
8,320,392 →
Application:
12/639,554 →
Method and Apparatus for Unified Final Buffer with Pointer-Based and Page-Based Scheme for Traffic Optimization
Patent:
8,850,089 →
Application:
12/818,767 →
Method And Apparatus To Optimize Class Of Service Under Multiple VCs With Mixed Reliable Transfer And Continuous Transfer Modes
Patent:
8,571,050 →
Application:
12/818,805 →
Method and Apparatus for a configurable packet routing, buffering and scheduling scheme to optimize throughput with deadlock prevention in SRIO-to-PCIe Bridges
Patent:
9,143,346 →
Application:
12/916,568 →
Method and Apparatus for a configurable packet routing, buffering and scheduling scheme to optimize throughput with deadlock prevention in SRIO-to-PCIe Bridges
Patent:
8,949,501 →
Application:
12/916,574 →
Method and Apparatus for a configurable packet routing, buffering and scheduling scheme to optimize throughput with deadlock prevention in SRIO-to-PCIe Bridges
Patent:
8,730,983 →
Application:
12/916,580 →
Method and Apparatus for Channel Equalization in High Speed S-Rio Based Communication Systems
Patent:
8,842,721 →
Application:
13/244,599 →
Long-Distance Rapidio Packet Delivery
Low Latency Interconnect Integrated Event Handling
Patent:
9,921,891 →
Application:
14/675,498 →
Scalable Coherent Apparatus and Method
Patent:
10,235,295 →
Application:
15/247,854 →
Long Range Beamforming and Steering in Wireless Communication Links
Long Range Beamforming and Steering in Wireless Communication Links
Buffer Management in Packet Switched Fabric Devices
Method and Apparatus for Selective Packet Discard
Patent:
8,238,339 →
Application:
12/712,477 →
Method and Apparatus for Adaptive Buffer Management for Traffic Optimization on Switches
Patent:
8,254,399 →
Application:
12/639,887 →
Related Assignments
(19)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Sep 19, 2012
From: BAWELL, SHAWN; MOURANT, JEAN-MARC; HUANG, FENG-JUNG
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 028982/0469 →
Assignment of Assignor's Interest
Sep 19, 2012
From: BAWELL, SHAWN; MOURANT, JEAN-MARC; HUANG, FENG-JUNG
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 028982/0440 →
Assignment of Assignor's Interest
Jun 5, 2014
From: BAWELL, SHAWN; MOURANT, JEAN-MARC; HUBERT, OLIVIER
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 033043/0555 →
Assignment of Assignor's Interest
Mar 28, 2015
From: KRISHNAMURTHI, KATHIRAVAN; BAWELL, SHAWN; MOURANT, JEAN-MARC; HUBERT, OLIVIER
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 035280/0425 →
Security Agreement
Apr 5, 2017
From: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; MAGNUM SEMICONDUCTOR, INC.; ENDWAVE CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 042166/0431 →
Employment Agreement
Sep 20, 2017
From: MOURANT, JEAN-MARC
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 043919/0980 →
Assignment of Assignor's Interest
Oct 3, 2017
From: MAO, CHUYING; LI, RAN
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 043768/0667 →
Release of Security Interest
Mar 29, 2019
From: JPMORGAN CHASE BANK, N.A.
To: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; CHIPX, INCORPORATED; ENDWAVE CORPORATION
Reel/Frame 048746/0001 →
Assignment of Assignor's Interest
Jun 11, 2021
From: GHADIRI SADRABADI, MOHAMMAD; KANAR, TUMAY
To: RENESAS ELECTRONICS AMERICA INC.
Reel/Frame 056511/0144 →
Assignment of Assignor's Interest
Dec 20, 2021
From: LADHANI, HUSSAIN HASANALI; SRINIDHI EMBAR, RAMANUJAM
To: RENESAS ELECTRONICS AMERICA INC.
Reel/Frame 058433/0454 →
Assignment of Assignor's Interest
Sep 28, 2022
From: KHATRI, HIMANSHU; ZIHIR, SAMET; KANAR, TUMAY
To: RENESAS ELECTRONICS AMERICA INC.
Reel/Frame 061237/0803 →
Assignment of Assignor's Interest
Dec 16, 2022
From: ABBASI, MORTEZA; KAMATH, ARJUN; KANAR, TUMAY
To: RENESAS ELECTRONICS AMERICA INC.
Reel/Frame 062126/0497 →
Assignment of Assignor's Interest
Sep 20, 2023
From: VAGUES, MARTIN ASHLEY
To: RENESAS ELECTRONICS AMERICA INC.
Reel/Frame 064970/0088 →
Assignment of Assignor's Interest
Dec 20, 2023
From: SRINIDHI EMBAR, RAMANUJAM; PEDNEKAR, PRATHAMESH HIRACHANDRA; WOHLMUTH, WALTER TONY
To: RENESAS ELECTRONICS AMERICA INC.
Reel/Frame 065923/0830 →
Assignment of Assignor's Interest
Jun 13, 2024
From: DARRAJI, RAMZI; SRINIDHI EMBAR, RAMANUJAM
To: RENESAS ELECTRONICS AMERICA INC.
Reel/Frame 067716/0800 →
Assignment of Assignor's Interest
Jul 23, 2024
From: SHUKLA, SHISHIR RAMASARE
To: RENESAS ELECTRONICS AMERICA INC.
Reel/Frame 068057/0516 →
Merger
Apr 15, 2025
From: INTEGRATED DEVICE TECHNOLOGY, INC.
To: RENESAS ELECTRONICS AMERICA INC.
Reel/Frame 070851/0391 →
Assignment of Assignor's Interest
Aug 19, 2025
From: DARRAJI, RAMZI; SRINIDHI EMBAR, RAMANUJAM
To: RENESAS ELECTRONICS AMERICA INC.
Reel/Frame 072058/0848 →
Assignment of Assignor's Interest
Sep 9, 2025
From: PEDNEKAR, PRATHAMESH HIRACHANDRA
To: RENESAS ELECTRONICS AMERICA INC.
Reel/Frame 072205/0294 →