Three-way combined RF power amplifier architecture

1. An apparatus comprising:

a circuit configured to convert an input radio frequency (RF) signal into a first RF signal, a second RF signal, and a third RF signal;

a carrier amplifier stage including a first transistor of a first size, wherein the first RF signal has a first power level that matches a power capacity of the first transistor, and the carrier amplifier stage is configured to amplify the first RF signal to generate a first amplified RF signal;

a first peaking amplifier stage including a second transistor of the first size, wherein the second RF signal has a second power level that matches a power capacity of the second transistor, and the first peaking amplifier stage is configured to amplify the second RF signal to generate a second amplified RF signal; and

a second peaking amplifier stage including a third transistor of a second size different from the first size, wherein the third RF signal has a third power level that matches a power capacity of the third transistor, and the second peaking amplifier stage is configured to amplify the third RF signal to generate a third amplified RF signal,

wherein the first amplified RF signal, the second amplified RF signal, and third amplified RF signal, are combined into an output RF signal, the output RF signal being an amplified version of the input RF signal, and

wherein the second size is double the first size such that a gate periphery ratio of the carrier amplifier stage, the first peaking amplifier stage and the second peaking amplifier stage is 1:1:2, and the carrier amplifier stage and the first peaking amplifier stage are impedance matched to a 2:1 ratio.

2. The apparatus of claim 1 , wherein:

the circuit comprises a first splitter, a second splitter, a first matching network, a second matching network, and a third matching network;

the first splitter being configured to split the input RF signal into a first split RF signal and an intermediate RF signal;

the second splitter being configured to split the intermediate RF signal into a second split RF signal and a third split RF signal;

the first matching network being configured to adjust a power level of the first split RF signal to the first power level to generate the first RF signal;

the second matching network being configured to adjust a power level of the second split RF signal to the second power level to generate the second RF signal; and

the third matching network being configured to adjust a power level of the third split RF signal to the third power level to generate the third RF signal.

3. The apparatus of claim 2 , wherein each one of the first matching network, the second matching network, and the third matching network, includes a respective harmonic trap to reduce harmonics of the first split RF signal, the second split RF signal, and the third split RF signal, respectively.

4. The apparatus of claim 1 , further comprising an output network configured to combine the first amplified RF signal, the second amplified RF signal, and third amplified RF signal to generate the output RF signal.

5. The apparatus of claim 1 , wherein the first transistor, the second transistor, and the third transistor are Gallium Nitride (GaN) transistors.

6. The apparatus of claim 1 , wherein the circuit comprises:

a first gain stage comprising a predriver configured to perform first amplification on the input RF signal;

a second gain stage comprising a driver configured to perform second amplification on an output from the first gain stage; and

at least one splitter configured to split an output from the second gain stage into the first RF signal, the second RF signal, and the third RF signal.

7. The apparatus of claim 1 , wherein the circuit comprises:

a first splitter configured to split the input RF signal into a first split RF signal having a quarter of power level of the input RF signal and an intermediate RF signal having three quarters of the power level of the input RF signal; and

a second splitter configured to split the intermediate RF signal in into a second split RF signal having a quarter of power level of the input RF signal and a third split RF signal having half of the power level of the input RF signal.

8. A method for amplifying a signal, the method comprising:

converting an input radio frequency (RF) signal into a first RF signal having a first power level that matches a power capacity of a first transistor of a first size in a carrier amplifier stage;

converting the input RF signal into a second RF signal having a second power level that matches a power capacity of a second transistor of the first size in a first peaking amplifier stage;

converting the input RF signal into a third RF signal having a third power level that matches a power capacity of a third transistor of a second size in a second peaking amplifier stage;

amplifying the first RF signal to generate a first amplified RF signal;

amplifying the second RF signal to generate a second amplified RF signal;

amplifying the third RF signal to generate a third amplified RF signal;

combining the first amplified RF signal, the second amplified RF signal, and third amplified RF signal, into an output RF signal that is an amplified version of the input RF signal, wherein the second size is double the first size such that a gate periphery ratio of the carrier amplifier stage, the first peaking amplifier stage and the second peaking amplifier stage is 1:1:2, wherein the carrier amplifier stage and the first peaking amplifier stage are impedance matched to a 2:1 ratio.

9. The method of claim 8 , wherein converting the input RF signal into the first RF signal, the second RF signal, and the third RF signal comprises:

splitting the input RF signal into a first split RF signal and an intermediate RF signal;

splitting the intermediate RF signal into a second split RF signal and a third split RF signal;

adjusting a power level of the first split RF signal to the first power level to generate the first RF signal;

adjusting a power level of the second split RF signal to the second power level to generate the second RF signal; and

adjusting a power level of the third split RF signal to the third power level to generate the third RF signal.

10. The method of claim 9 , further comprising reducing harmonics of the first split RF signal, the second split RF signal, and the third split RF signal, using harmonics traps.

11. The method of claim 8 , wherein the first transistor, the second transistor, and the third transistor are Gallium Nitride (GaN) transistors.

12. The method of claim 8 , further comprising:

operating a first gain stage to perform first amplification on the input RF signal;

operating a second gain stage to perform second amplification on an output from the first gain stage; and

splitting an output from the second gain stage into the first RF signal, the second RF signal, and the third RF signal.

13. The method of claim 8 , further comprising:

splitting the input RF signal into a first split RF signal having a quarter of power level of the input RF signal and an intermediate RF signal having three quarters of the power level of the input RF signal; and

splitting the intermediate RF signal in into a second split RF signal having a quarter of power level of the input RF signal and a third split RF signal having half of the power level of the input RF signal.

14. An apparatus comprising:

a transmitter configured to receive an input RF signal; and

an amplifier connected to the transmitter, wherein the amplifier comprises:

a circuit configured to convert an input radio frequency (RF) signal into a first RF signal, a second RF signal, and a third RF signal;

a carrier amplifier stage including a first transistor of a first size, wherein the first RF signal has a first power level that matches a power capacity of the first transistor, and the carrier amplifier stage is configured to amplify the first RF signal to generate a first amplified RF signal;

a first peaking amplifier stage including a second transistor of the first size, wherein the second RF signal has a second power level that matches a power capacity of the second transistor, and the first peaking amplifier stage is configured to amplify the second RF signal to generate a second amplified RF signal; and

a second peaking amplifier stage including a third transistor of a second size different from the first size, wherein the third RF signal has a third power level that matches a power capacity of the third transistor, and the second peaking amplifier stage is configured to amplify the third RF signal to generate a third amplified RF signal,

wherein the first amplified RF signal, the second amplified RF signal, and third amplified RF signal, are combined into an output RF signal, the output RF signal being an amplified version of the input RF signal, and

wherein the second size is double the first size such that a gate periphery ratio of the carrier amplifier stage, the first peaking amplifier stage and the second peaking amplifier stage is 1:1:2, wherein the carrier amplifier stage and the first peaking amplifier stage are impedance matched to a 2:1 ratio.

15. The apparatus of claim 14 , wherein:

the circuit comprises a first splitter, a second splitter, a first matching network, a second matching network, and a third matching network;

the first splitter being configured to split the input RF signal into a first split RF signal and an intermediate RF signal;

the second splitter being configured to split the intermediate RF signal into a second split RF signal and a third split RF signal;

the first matching network being configured to adjust the first split RF signal to generate the first RF signal;

the second matching network being configured to adjust the second split RF signal to generate the second RF signal; and

the third matching network being configured to adjust the third split RF signal to generate the third RF signal.

16. The apparatus of claim 15 , wherein each one of the first matching network, the second matching network, and the third matching network, includes a respective harmonic trap to reduce harmonics of the first split RF signal, the second split RF signal, and the third split RF signal, respectively.

17. The apparatus of claim 14 , further comprising an output network configured to combine the first amplified RF signal, the second amplified RF signal, and third amplified RF signal to generate the output RF signal.

18. The apparatus of claim 14 , wherein the first transistor, the second transistor, and the third transistor are Gallium Nitride (GaN) transistors.

19. The apparatus of claim 14 , wherein the circuit comprises:

a first gain stage comprising a predriver configured to perform first amplification on the input RF signal;

a second gain stage comprising a driver configured to perform second amplification on an output form the first gain stage; and

at least one splitter configured to split an output from the second gain stage into the first RF signal, the second RF signal, and the third RF signal.

20. The apparatus of claim 14 , wherein the circuit comprises:

a first splitter configured to split the input RF signal into a first split RF signal having a quarter of power level of the input RF signal and an intermediate RF signal having three quarters of the power level of the input RF signal; and

a second splitter configured to split the intermediate RF signal in into a second split RF signal having a quarter of power level of the input RF signal and a third split RF signal having half of the power level of the input RF signal.