THREE STAGE POWER AMPLIFIER WITH PEAK OUTPUT MATCH
Systems and circuits implementing an amplifier module are described. An integrated circuit can include a pre-driver stage, a driver stage and a final stage. The pre-driver stage can amplify an input signal to generate a first amplified signal. The driver stage can amplify the first amplified signal to generate a second amplified signal. The final stage can amplify the second amplified signal to generate an output amplified signal. The final stage can include a peak amplifier, a main amplifier, a peak input matching network, a peak output matching network, a main input matching network and a main output matching network. The peak output network can include a first matching section and a second matching section. The first matching section and the second matching section can perform different impedance matching. The main input matching network can include a harmonic trapping that traps a second harmonic of the second amplified signal.
1 . An integrated circuit comprising:
a pre-driver stage configured to amplify an input signal to generate a first amplified signal;
a driver stage configured to amplify the first amplified signal to generate a second amplified signal; and
a final stage configured to amplify the second amplified signal to generate an output amplified signal, wherein the final stage comprises:
a peak amplifier;
a main amplifier;
a peak input matching network;
a peak output matching network comprising a first matching section and a second matching section, wherein the first matching section and the second matching section perform different impedance matching;
a main input matching network comprising a harmonic trapping section configured to trap a second harmonic of the second amplified signal; and
a main output matching network.
2 . The integrated circuit of claim 1 , wherein the final stage is implemented by a Doherty amplifier comprising a first GaN device configured as the peak amplifier and a second GaN device configured as the main amplifier.
3 . The integrated circuit of claim 1 , wherein the first matching section and the second matching section of the peak output matching network are implemented by at least one of microstrip lines and lump elements.
4 . The integrated circuit of claim 1 , wherein the harmonic trapping section of the main input matching network is implemented by a LC circuit in a shunt arrangement.
5 . The integrated circuit of claim 1 , wherein the pre-driver stage is implemented by a Gallium Arsenide (GaAs) device.
6 . The integrated circuit of claim 1 , wherein the driver stage comprises:
a first hybrid coupler configured to:
split the first amplified signal into a first intermediate signal and a second intermediate signal;
absorb reflections resulted from mismatches between the first intermediate signal and the second intermediate signal;
a first amplifier configured to amplify the first intermediate signal to generate a first amplified intermediate signal;
a second amplifier configured to amplify the second intermediate signal to generate a second amplified intermediate signal;
a second hybrid coupler configured to:
absorb reflections resulted from mismatches between the first amplified intermediate signal and the second amplified intermediate signal; and
combine the first amplified intermediate signal and the second intermediate amplified signal to generate the second amplified signal.
7 . The integrated circuit of claim 6 , wherein the first hybrid coupler and the second hybrid coupler are quadrature couplers.
8 . A system comprising:
a plurality of antennas;
a plurality of transmission channels, wherein a transmission channel comprises an amplifier module comprising:
a pre-driver stage configured to amplify an input signal to generate a first amplified signal;
a driver stage configured to amplify the first amplified signal to generate a second amplified signal; and
a final stage configured to amplify the second amplified signal to generate an output amplified signal, wherein the final stage comprises:
a peak amplifier;
a main amplifier;
a peak input matching network;
a peak output matching network comprising a first matching section and a second matching section, wherein the first matching section and the second matching section perform different impedance matching;
a main input matching network comprising a harmonic trapping section configured to trap a second harmonic of the second amplified signal; and
a main output matching network.
9 . The system of claim 8 , wherein the final stage is implemented by a Doherty amplifier comprising a first GaN device configured as the peak amplifier and a second GaN device configured as the main amplifier.
10 . The system of claim 9 , wherein the first matching section and the second matching section of the peak output matching network are implemented by at least one of microstrip lines and lump elements.
11 . The system of claim 9 , wherein the harmonic trapping section of the main input matching network is implemented by a LC circuit in a shunt arrangement.
12 . The system of claim 8 , wherein the pre-driver stage is implemented by a Gallium Arsenide (GaAs) device.
13 . The system of claim 8 , wherein the driver stage comprises:
a first hybrid coupler configured to:
split the first amplified signal into a first intermediate signal and a second intermediate signal;
absorb reflections resulted from mismatches between the first intermediate signal and the second intermediate signal;
a first amplifier configured to amplify the first intermediate signal to generate a first amplified intermediate signal;
a second amplifier configured to amplify the second intermediate signal to generate a second amplified intermediate signal;
a second hybrid coupler configured to:
absorb reflections resulted from mismatches between the first amplified intermediate signal and the second amplified intermediate signal; and
combine the first amplified intermediate signal and the second intermediate amplified signal to generate the second amplified signal.
14 . The system of claim 13 , wherein the first hybrid coupler and the second hybrid coupler are quadrature couplers.
15 . A system comprising:
a plurality of antennas;
a plurality of receiver channels configured to process signals being received by the plurality of antennas;
a plurality of transmission channels, wherein a transmission channel comprises an amplifier module comprising:
a pre-driver stage configured to amplify an input signal to generate a first amplified signal;
a driver stage configured to amplify the first amplified signal to generate a second amplified signal; and
a final stage configured to amplify the second amplified signal to generate an output amplified signal, wherein the final stage comprises:
a peak amplifier;
a main amplifier;
a peak input matching network;
a peak output matching network comprising a first matching section and a second matching section, wherein the first matching section and the second matching section perform different impedance matching;
a main input matching network comprising a harmonic trapping section configured to trap a second harmonic of the second amplified signal; and
a main output matching network.
16 . The system of claim 15 , wherein the final stage is implemented by a Doherty amplifier comprising a first GaN device configured as the peak amplifier and a second GaN device configured as the main amplifier.
17 . The system of claim 16 , wherein the first matching section and the second matching section of the peak output matching network are implemented by at least one of microstrip lines and lump elements.
18 . The system of claim 16 , wherein the harmonic trapping section of the main input matching network is implemented by a LC circuit in a shunt arrangement.
19 . The system of claim 15 , wherein the driver stage comprises:
a first hybrid coupler configured to:
split the first amplified signal into a first intermediate signal and a second intermediate signal;
absorb reflections resulted from mismatches between the first intermediate signal and the second intermediate signal;
a first amplifier configured to amplify the first intermediate signal to generate a first amplified intermediate signal;
a second amplifier configured to amplify the second intermediate signal to generate a second amplified intermediate signal;
a second hybrid coupler configured to:
absorb reflections resulted from mismatches between the first amplified intermediate signal and the second amplified intermediate signal; and
combine the first amplified intermediate signal and the second intermediate amplified signal to generate the second amplified signal.
20 . The system of claim 19 , wherein the first hybrid coupler and the second hybrid coupler are quadrature couplers.