IP Library Granted Patent US 8,238,339
Granted Patent B1
US 8,238,339 · App. 12/712,477 · Granted Aug 7, 2012

Method and apparatus for selective packet discard

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Quick Facts
Patent No.
US 8,238,339
App. No.
12/712,477
Granted
Aug 7, 2012
Kind
B1
Abstract

A method and apparatus for selective packet discard have been disclosed where two bits are added to a packet to indicate various discard options.

Claims (39)

1. A method comprising:

forwarding a packet through a switch as soon as a Start Of Packet delimiter (SOP) is received for said packet;

inserting one or more discard bits at an End of Packet (EOP) cycle for said packet wherein said one or more discard bits request said packet cancellation upon a condition selected from the group consisting of a pattern not match with trace enabled, a pattern match with packet filter enabled, and any detected error;

storing said one or more discard bits in a memory, wherein said storing is to a memory location indexed through a transmitted packet index;

generating a STOMP Control Symbol based on said one or more discard bits and a configuration of an Egress Port (EP), wherein said STOMP Control Symbol requests a Link Partner to cancel said packet;

receiving from said Link Partner a Not Accepted Control Symbol (NACK) along with an Acknowledgement Indentification (ACK ID); and

retrieving said stored said one or more discard bits from said memory;

comparing said retrieved said stored said one or more discard bits from said memory against said configuration of said EP; and

releasing said memory used to store said one or more discard bits and discarding said packet.

2. The method of claim 1 further comprising:

receiving said packet on an n-port Switch, said n-port switch consisting of n Ingress Ports (IP) wherein each of said n IP has an Input Buffer (IB) for said packet reception;

storing said received packet into one of said n IB;

forwarding said received packet to one or more n Crosspoint Buffers (CB), wherein each of said n CB corresponds to a corresponding n Egress Port;

forwarding said received packet from said one or more n CB through one or more said n Egress Port to one or more Link Partner, wherein each of said n Egress Port has a Final Buffer.

3. The method of claim 1 wherein said pattern not match with trace enabled, and said pattern match with packet filter enabled, and said any detected error are performed after said SOP received for said packet.

4. The method of claim 2 wherein said configuration of said Egress Port is selected from the group consisting of a normal forwarding port, and a trace port.

5. The method of claim 4 further comprising:

setting a discard_trace bit when said condition pattern not match with trace enabled exists; and

discarding said received packet forwarded to said trace port when said discard_trace bit is set.

6. The method of claim 4 further comprising:

setting a discard_normal bit when said condition pattern match with packet filter enabled exists; and

discarding said received packet forwarded to said normal forwarding port when said discard_normal bit is set.

7. The method of claim 4 further comprising:

setting a discard_normal bit when said condition any detected error exists;

setting a discard_trace bit when said condition any detected error exists;

discarding said received packet forwarded to said trace port when said discard_trace bit is set and said discard_trace bit is set; and

discarding said received packet forwarded to said normal forwarding port when said discard_trace bit is set and said discard_trace bit is set.

8. The method of claim 5 further comprising:

transmitting said generated STOMP Control Symbol from said EP to said Link Partner after said packet has been transmitted from said EP to said Link Partner.

9. The method of claim 6 further comprising:

transmitting said generated STOMP Control Symbol from said EP to said Link Partner after said packet has been transmitted from said EP to said Link Partner.

10. The method of claim 7 further comprising:

transmitting said generated STOMP Control Symbol from said EP to said Link Partner after said packet has been transmitted from said EP to said Link Partner.

11. The method of claim 1 wherein said one or more discard bits are discard_normal and discard_trace and wherein said storing is during a time when said packet is being transmitted out of said EP and wherein said storing is selected through said transmitted packet index for a transmitted said packet.

12. The method of claim 1 further comprising:

generating said Not Accepted Control Symbol (NACK) and said ACK ID in response to said Link Partner receiving said STOMP Control Symbol, wherein said ACK ID is a packet index; and

requesting retransmission of said packet based upon said packet index.

13. The method of claim 12 wherein retrieving said stored said one or more discard bits from said memory is from said EP based upon said packet index; and wherein said releasing said memory used to store said one or more discard bits and discarding said packet is based upon a logic condition selected from the group consisting of discard_trace is set and said EP is configured as a trace port, discard_normal is set and said EP is not configured as a trace port, and discard_trace is set and discard_normal is set.

14. The method of claim 1 wherein said one or more discard bits are two bits denoted discard_trace and discard_normal and wherein said switch has one or more ports.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2025
From: RENESAS ELECTRONICS AMERICA INC.
To: AXIRO SEMICONDUCTOR INC.
Reel/Frame 070864/0142 →
MERGER Recorded Apr 15, 2025
From: INTEGRATED DEVICE TECHNOLOGY, INC.
To: RENESAS ELECTRONICS AMERICA INC.
Reel/Frame 070851/0391 →
RELEASE OF SECURITY INTEREST Recorded Mar 29, 2019
From: JPMORGAN CHASE BANK, N.A.
To: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; CHIPX, INCORPORATED; ENDWAVE CORPORATION; MAGNUM SEMICONDUCTOR, INC.
Reel/Frame 048746/0001 →
SECURITY AGREEMENT Recorded Apr 5, 2017
From: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; MAGNUM SEMICONDUCTOR, INC.; ENDWAVE CORPORATION; CHIPX, INCORPORATED
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 042166/0431 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 25, 2010
From: WANG, CHI-LIE; MO, JASON Z
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 023991/0671 →