Error management system and method for a packet switch

1. A packet switch integrated circuit, comprising:

an error management module; and

at least one component configured to facilitate routing of data packets through the packet switch and to generate a first plurality of error codes, each error code of the plurality of error codes identifying an error occurring in the packet switch, the at least one component further configured to provide the first plurality of error codes to the error management module, the error management module configured to select at least one error code in the first plurality of error codes and to generate an error log in the packet switch comprising the at least one selected error code, wherein a first component of the at least one component is configured to generate a first error code of the at least one selected error code, the error management module is further configured to generate an acknowledgment based on the first error code, the first component is further configured to receive the acknowledgement, and the first component is inhibited from providing the first error code to the error management module more than once before the first component receives the acknowledgement.

2. The packet switch of claim 1 , wherein the first component is inhibited from generating the first error code more than once before the first component receives the acknowledgment.

3. The packet switch of claim 1 , wherein each error code of the first plurality of error codes identifies a component of the at least one component and an error occurring in the component.

4. The packet switch of claim 1 , wherein the error management module is further configured to filter the first plurality of error codes by identifying the at least one selected error code in a second plurality of error codes.

5. The packet switch of claim 4 , wherein the second plurality of error codes is configurable.

6. The packet switch of claim 1 , wherein the at least one component comprises:

a switching fabric for routing data packets;

a packet processor for processing data packets; and

an interface coupled to the switching fabric and the packet processor, the interface configured to receive a data packet and to route the data packet to either the switching fabric or the packet processor based on a destination identifier in the data packet.

7. A method for managing errors in a packet switch, the method comprising:

generating a first plurality of error codes by at least one component of the packet switch, each error code of the plurality of error codes identifying an error occurring in the packet switch;

selecting at least one error code in the first plurality of error codes, wherein a first error code of the at least one selected error code is generated by a first component of the at least one component;

receiving the first error code at an error management module of the packet switch;

generating an error log in the packet switch, the error log comprising the at least one selected error code;

generating an acknowledgment in response to receiving the first error code;

receiving the acknowledgment at the first component; and

inhibiting the first component from providing the first error code to the error management module more than once before receiving the acknowledgment at the first component.

8. The method of claim 7 , further comprising inhibiting the first component from generating the first error code more than once before receiving the acknowledgment at the first component.

9. The method of claim 7 , wherein each error code of the first plurality of error codes identifies a component of the at least one component and an error occurring in the component.

10. The method of claim 7 , wherein selecting the at least one error code comprises identifying a first error code of the at least one selected error code in a second plurality of error codes.

11. A packet switch integrated circuit comprising:

means in the packet switch for routing data packets through the packet switch;

means in the packet switch for generating a plurality of error codes, each error code of the plurality of error codes identifying an error occurring in the packet switch;

means in the packet switch for selecting at least one error code in the plurality of error codes, wherein a first error code of the at least one selected error code is generated by a component of the packet switch;

means in the packet switch for generating an error log based on the at least one selected error code;

means in the packet switch for receiving the first error code from the component of the packet switch;

means in the packet switch for generating an acknowledgement in response to receiving the first error code from the component of the packet switch; and

means in the packet switch for inhibiting the component from generating the first error code more than once before the component receives the acknowledgement.

12. The packet switch of claim 11 , further comprising means for processing data packets.

13. A system comprising:

a packet switch configured to preprocess data packets by performing operations on data payloads of the data packets to facilitate baseband processing operations on the data packets, the packet switch comprising:

an error management module; and

at least one component of the packet switch configured to facilitate routing of data packets through the packet switch and to generate a first plurality of error codes, each error code of the plurality of error codes identifying an error occurring in the packet switch, the at least one component further configured to provide the first plurality of error codes to the error management module, the error management module configured to select at least one error code in the first plurality of error codes and to generate an error log in the packet switch comprising the at least one selected error code, wherein a first component of the at least one component is configured to generate a first error code of the at least one selected error code, the error management module is further configured to generate an acknowledgment based on the first error code, the first component is further configured to receive the acknowledgement, and the first component is inhibited from providing the first error code to the error management module more than once before the first component receives the acknowledgement; and

at least one signal processor coupled to the packet switch, the at least one signal processor configured to receive the preprocessed data packets from the packet switch and to further process the data packets by performing baseband processing operations on the data payloads of the data packets.

14. The packet switch of claim 1 , wherein the packet switch further comprises a packet processor configured to preprocess the data packets by performing operations on data payloads of the data packets to facilitate baseband processing operations on the data packets.

15. The packet switch of claim 14 , wherein the first component is the packet processor.

16. The method of claim 7 , further comprising preprocessing the data packets in the packet switch by performing operations on data payloads of the data packets to facilitate baseband processing operations on the data packets.

17. The method of claim 16 , further comprising performing baseband processing operations on the data payloads of the data packets to further process the data packets.

18. The method of claim 7 , wherein the at least one component comprises a switching fabric for routing data packets, a packet processor for processing data packets, and an interface coupled to the switching fabric and the packet processor, the method further comprising:

receiving a data packet at the interface; and

routing the data packet to either the switching fabric or the packet processor based on a destination identifier in the data packet.

19. The packet switch of claim 11 , further comprising means for preprocessing the data packets by performing operations on data payloads of the data packets to facilitate baseband processing operations on the data packets.

20. The system of claim 13 , wherein the at least one component comprises:

a switching fabric for routing data packets;

a packet processor for processing data packets; and

an interface coupled to the switching fabric and the packet processor, the interface configured to receive a data packet and to route the data packet to either the switching fabric or the packet processor based on a destination identifier in the data packet.