Method and apparatus for congestion and fault management with time-to-live
View Patent ↗A method and apparatus for congestion and fault management with time-to-live (TTL) have been disclosed. Each time a packet is transferred into an Egress Port's Final Buffer, an associated TTL Timeout Counter will be loaded with a value. If the packet cannot be transferred out of the Egress Port before TTL timeout, it will be purged by removing a memory buffer pointer from the corresponding Virtual Output Queue (VOQ) entry.
1. An apparatus comprising:
a plurality of ingress ports, wherein each of said plurality of ingress ports has a plurality of ingress buffers:
a switch fabric having a plurality of crosspoint buffers, wherein one or more of said plurality of ingress ports is in operative communication with one or more of said plurality of crosspoint buffers;
a plurality of egress ports, wherein each of said plurality of egress ports has a plurality of egress buffers, wherein one or more of said plurality of egress ports is in operative communication with one or more of said plurality of crosspoint buffers;
a time-to-live logic block for each of said plurality of egress ports and in operative communication with said each of said plurality of egress ports; and
a set of time-to-live registers for each of said time-to-live logic block for each of said plurality of egress ports and in operative communication with said each of said time-to-live logic block.
2. An apparatus comprising:
a plurality of ingress ports, wherein each of said plurality of ingress ports has a plurality of ingress buffers;
a switch fabric having a plurality of crosspoint buffers, wherein one or more of said plurality of ingress ports is in operative communication with one or more of said plurality of crosspoint buffers;
a plurality of egress ports, wherein each of said plurality of egress ports has a plurality of egress buffers, wherein one or more of said plurality of egress ports is in operative communication with one or more of said plurality of crosspoint buffers;
a time-to-live logic block for each of said plurality of egress ports and in operative communication with said each of said plurality of egress ports;
a set of time-to-live registers for each of said time-to-live logic block for each of said plurality of egress ports and in operative communication with said each of said time-to-live logic block; and
a clock, said clock in operative communication with said set of time-to-live registers.