IP Library Granted Patent US 7,805,551
Granted Patent B2
US 7,805,551 · App. 11/863,184 · Granted Sep 28, 2010

Multi-function queue to support data offload, protocol translation and pass-through FIFO

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Quick Facts
Patent No.
US 7,805,551
App. No.
11/863,184
Granted
Sep 28, 2010
Kind
B2
Abstract

A multi-port serial buffer having a plurality of queues is configured to include a first set of queues assigned to store write data associated with a first port, and a second set of queues assigned to store write data associated with a second port. The available queues are user-assignable to either the first set or the second set. Write operations to the first set of queues can be performed in parallel with write operations to the second programmable set of queues. In addition, a first predetermined set of queues is assigned to the first port for read operations, and a second predetermined set of queues is assigned to the second port for read operations. Data can be read from the first predetermined set of queues to the first port at the same time that data is read from the second predetermined set of queues to the second port.

Claims (40)

1. A serial buffer comprising:

a first serial port;

a second serial port;

a plurality of queues;

a first write block configured to perform write operations associated with the first serial port by accessing a first programmable set of the plurality of queues;

a second write block configured to perform write operations associated with the second serial port by accessing a second programmable set of the plurality of queues, wherein the first programmable set and the second programmable set are mutually exclusive;

a first read block configured to perform read operations associated with the first serial port by accessing a first predetermined set of the plurality of queues; and

a second read block configured to perform read operations associated with the second serial port by accessing a second predetermined set of the plurality of queues.

2. The serial buffer of claim 1 , wherein the first programmable set of the plurality of queues is selected to be the same as the first predetermined set of the plurality of queues.

3. The serial buffer of claim 2 , wherein the second programmable set of the plurality of queues is selected to be the same as the second predetermined set of the plurality of queues.

4. The serial buffer of claim 1 , wherein the first programmable set of the plurality of queues is selected to be the same as the second predetermined set of the plurality of queues.

5. The serial buffer of claim 4 , wherein the second programmable set of the plurality of queues is selected to be the same as the first predetermined set of the plurality of queues.

6. The serial buffer of claim 4 , wherein the first serial port is configured to implement a first serial buffer protocol and the second serial port is also configured to implement the first serial buffer protocol.

7. The serial buffer of claim 4 , wherein the first serial port is configured to implement a first serial buffer protocol and the second serial port is also configured to implement a second serial buffer protocol, different than the first serial buffer protocol.

8. The serial buffer of claim 1 , wherein the first serial port is configured to implement a first serial buffer protocol and the second serial port is also configured to implement the first serial buffer protocol.

9. The serial buffer of claim 1 , wherein the first serial port is configured to implement a first serial buffer protocol and the second serial port is also configured to implement a second serial buffer protocol, different than the first serial buffer protocol.

10. The serial buffer of claim 1 , wherein the first write block is configured to perform write operations in parallel with the second write block.

11. The serial buffer of claim 1 , wherein the first read block is configured to perform read operations in parallel with the second read block.

12. The serial buffer of claim 1 , wherein the first write block comprises means for performing a write operation associated with the first serial port by simultaneously accessing a plurality of queues in the first programmable set.

13. The serial buffer of claim 12 , wherein the second write block comprises means for performing a write operation associated with the second serial port by simultaneously accessing a plurality of queues in the second programmable set.

14. The serial buffer of claim 1 , wherein the first write block is configured to perform write operations in parallel with read operations performed by the first read block.

15. The serial buffer of claim 14 , wherein the second write block is configured to perform write operations in parallel with read operations performed by the second read block.

16. The serial buffer of claim 1 , further comprising a configuration register for storing a plurality of configuration bits, wherein each of the configuration bits is associated with a corresponding one of the queues, and determines whether the corresponding one of the queues is in the first programmable set of queues or the second programmable set of queues.

17. The serial buffer of claim 1 , wherein the first write block is configured to perform write operations to a first one of the queues in parallel with read operations performed by the second read block from the first one of the queues.

18. The serial buffer of claim 17 , wherein the second write block is configured to perform write operations to a second one of the queues in parallel with read operations performed by the first read block from the second one of the queues.

19. A method of operating a serial buffer comprising:

selecting a first set of one or more queues from a plurality of queues to correspond with a first serial port of the serial buffer;

selecting a second set of one or more queues from the plurality of queues to correspond with a second serial port of the serial buffer, wherein any of the plurality of queues can be selected to be in either the first set or the second set, and wherein the first set of one or more queues and the second set of one or more queues are mutually exclusive;

performing write operations to the first set of one more queues in response to write requests received on the first serial port;

performing write operations to the second set of one or more queues in response to write requests received on the second serial port;

performing read operations from a first predetermined set of the plurality of queues in response to read requests received on the first serial port; and

performing read operations from a second predetermined set of the plurality of queues in response to read requests received on the second serial port.

20. The method of claim 19 , further comprising selecting the first set of one or more queues to be the same as the second predetermined set of the plurality of queues.

21. The method of claim 20 , further comprising selecting the second set of one or more queues to be the same as the second predetermined set of the plurality of queues.

22. The method of claim 19 , wherein the first serial port is configured to implement a first serial buffer protocol and the second serial port is also configured to implement a second serial buffer protocol, different than the first serial buffer protocol.

23. The method of claim 19 , further comprising:

performing write operations to the first set of one or more queues in parallel with write operations to the second set of one or more queues;

performing read operations from the first predetermined set of the plurality of queues in parallel with read operations from the second predetermined set of the plurality of queues;

performing write operations to the first set of one or more queues in parallel with read operations from the first predetermined set of the plurality of queues; and

performing write operations to the second set of one or more queues in parallel with read operations from the second predetermined set of the plurality of queues.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2025
From: RENESAS ELECTRONICS AMERICA INC.
To: AXIRO SEMICONDUCTOR INC.
Reel/Frame 070864/0142 →
MERGER Recorded Apr 15, 2025
From: INTEGRATED DEVICE TECHNOLOGY, INC.
To: RENESAS ELECTRONICS AMERICA INC.
Reel/Frame 070851/0391 →
RELEASE OF SECURITY INTEREST Recorded Mar 29, 2019
From: JPMORGAN CHASE BANK, N.A.
To: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; CHIPX, INCORPORATED; ENDWAVE CORPORATION; MAGNUM SEMICONDUCTOR, INC.
Reel/Frame 048746/0001 →
SECURITY AGREEMENT Recorded Apr 5, 2017
From: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; MAGNUM SEMICONDUCTOR, INC.; ENDWAVE CORPORATION; CHIPX, INCORPORATED
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 042166/0431 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 1, 2007
From: WANG, CHI-LIE; MO, JASON Z.; AU, MARIO
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 019904/0891 →