IP Library Granted Patent US 10,763,913
Granted Patent B1
US 10,763,913 · App. 16/372,698 · Granted Sep 1, 2020

Linear-in-dB log-amp with calibration for power detection

Inventors: Himanshu Khatri (San Diego, CA); Samet Zihir (San Diego, CA); Tumay Kanar (San Diego, CA)
Assignee: Integrated Device Technology, Inc.
H04B1/44H03F3/04H03F3/19H03G3/3036H04B1/04H04B1/18
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Quick Facts
Patent No.
US 10,763,913
App. No.
16/372,698
Granted
Sep 1, 2020
Kind
B1
Abstract

An apparatus includes a log amplifier and a calibration circuit. The log amplifier may be configured to generate an output signal in response to an offset between a first voltage and a second voltage. The calibration circuit may be configured to disconnect an input power and perform a cancellation of the offset when the input power is not present. The first voltage may be generated by the apparatus in response to a power detection. The second voltage may be received from a reference circuit. The cancellation of the offset may extend a working range of the apparatus. The output may provide a linear-in-dB power detection.

Claims (27)

1. An apparatus comprising:

a log amplifier circuit configured to generate an output signal in response to an offset between a first voltage and a second voltage; and

a calibration circuit configured to (i) disconnect an input power and (ii) perform a cancellation of said offset when said input power is not present,

wherein

(a) said first voltage is generated by said apparatus in response to a power detection,

(b) said second voltage is received from a reference circuit,

(c) said cancellation of said offset extends a working range of said apparatus,

(d) said output signal provides a linear-in-dB power detection,

(e) said calibration circuit comprises a comparison circuit configured to determine a difference between said first voltage and said second voltage when said input power is not present,

(f) said difference is used to control one or more programmable current sources, and

(g) said cancellation is performed by adjusting said programmable current sources in response to said difference.

2. The apparatus according to claim 1 , wherein said log amplifier circuit is configured to enable a log correction in an analog domain.

3. The apparatus according to claim 1 , wherein said working range is extended by setting said first voltage slightly lower than said second voltage.

4. The apparatus according to claim 1 , wherein said calibration circuit is configured to disconnect said input power and perform said cancellation in an open loop configuration.

5. The apparatus according to claim 4 , wherein said calibration circuit enables said open loop configuration by closing a first switch to disconnect said input power and opening a second switch to disable an amplifier.

6. The apparatus according to claim 1 , wherein said cancellation is performed by an open-loop mechanism.

7. The apparatus according to claim 1 , wherein said cancellation is performed by a closed-loop mechanism.

8. The apparatus according to claim 1 , wherein said cancellation reduces said offset or eliminates said offset.

9. The apparatus according to claim 1 , wherein (i) said apparatus is configured to generate said linear-in-dB power detection in a closed loop configuration and (ii) perform a calibration of said offset in an open loop configuration.

10. The apparatus according to claim 1 , wherein (i) said linear-in-dB power detection is provided to a controller circuit and (ii) said controller circuit is configured to adjust a power level of a transceiver circuit in response to said linear-in-dB power detection.

11. The apparatus according to claim 1 , wherein (i) said difference is used to control a first current source for said first voltage and a second current source for said second voltage, (ii) said first current source and said second current source are implemented using FET transistors in a P-channel configuration and (iii) said cancellation is performed by adjusting a strength of said first current source and said second current source in response to said difference.

12. The apparatus according to claim 1 , wherein (i) said difference is used to control a first current of a first input device and a second current of a second input device, (ii) said first input device and said second input device are implemented using transistors in a NPN configuration and (iii) said cancellation is performed by adjusting a strength of said first current and said second current in response to said difference.

13. The apparatus according to claim 1 , wherein (i) said difference is used to control a first bias voltage of a first current source and a second bias voltage of a second current source and (ii) said cancellation is performed by adjusting said first bias voltage and said second bias voltage in response to said difference.

14. The apparatus according to claim 1 , wherein said working range of said apparatus is extended by approximately 5 dB to 10 dB.

15. The apparatus according to claim 1 , wherein said calibration circuit disconnects said input power in response to an input from a controller.

16. The apparatus according to claim 15 , wherein said controller provides said input at a startup time of a phased array antenna panel.

17. The apparatus according to claim 1 , configured to implement a linear-in-dB log-amp with calibration for power detection.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2025
From: RENESAS ELECTRONICS AMERICA INC.
To: AXIRO SEMICONDUCTOR INC.
Reel/Frame 070864/0142 →
MERGER Recorded Apr 15, 2025
From: INTEGRATED DEVICE TECHNOLOGY, INC.
To: RENESAS ELECTRONICS AMERICA INC.
Reel/Frame 070851/0391 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 2, 2019
From: KHATRI, HIMANSHU; ZIHIR, SAMET; KANAR, TUMAY
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 048765/0620 →