IP Library Granted Patent US 10,686,258
Granted Patent B2
US 10,686,258 · App. 16/121,891 · Granted Jun 16, 2020

Hard-wired address for phased array antenna panels

Inventors: Samet Zihir (San Diego, CA); Tumay Kanar (San Diego, CA); Naveen Krishna Yanduru (San Diego, CA)
Assignee: Integrated Device Technology, Inc.
H01Q21/22H01Q1/26H01Q3/28H01Q3/36H01Q3/40H01Q3/46H01Q21/0025H01Q21/065H01Q21/067H01Q21/205H01Q21/24H03F3/195H03F3/245H03F3/4508H03F3/45085H04B1/401H04B1/44H04B7/0617H04B7/0682H04B7/0691H03F2200/09H03F2200/129H03F2200/144H03F2200/27H03F2200/387H03F2200/451H03F2203/45116H03F2203/45151H03F2203/45302H03F2203/45394H03F2203/45512H03F2203/45526H03F2203/45528
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Quick Facts
Patent No.
US 10,686,258
App. No.
16/121,891
Granted
Jun 16, 2020
Kind
B2
Abstract

An apparatus includes a phased array antenna panel and a plurality of beam former circuits. The phased array antenna panel generally comprises a plurality of antenna elements. The plurality of beam former circuits are each mounted on the phased array antenna panel adjacent to a number of the antenna elements. Each beam former circuit has one or more ports directly coupled to each of the adjacent antenna elements. Each beam former circuit may be configured to generate a plurality of radio-frequency output signals at the ports while in a transmit mode and receive a plurality of radio-frequency input signals at the ports while in a receive mode. Each beam former circuit generally implements a hard-wired address.

Claims (27)

1. An apparatus comprising:

a phased array antenna panel comprising a plurality of antenna elements; and

a plurality of beam former circuits (i) each mounted on said phased array antenna panel adjacent to a number of said antenna elements, (ii) each having one or more ports directly coupled to each of the adjacent antenna elements, (iii) each configured to generate a plurality of radio-frequency output signals at said ports while in a transmit mode, (iv) each configured to receive a plurality of radio-frequency input signals at said ports while in a receive mode, and (v) each implementing a hard-wired address.

2. The apparatus according to claim 1 , wherein said hard-wired address of each of said beam former circuits is set during manufacture of the beam former circuits.

3. The apparatus according to claim 2 , wherein said hard-wired address is programmed within an integrated circuit implementing the beam former circuits.

4. The apparatus according to claim 3 , wherein said hard-wired address is programmed using fuses within the integrated circuit implementing the beam former circuits.

5. The apparatus according to claim 3 , wherein said hard-wired address is programmed using anti-fuses within the integrated circuit implementing the beam former circuits.

6. The apparatus according to claim 1 , wherein said hard-wired address is set by tying a number of address pins of each of the beam former circuits to either a supply voltage or a ground potential of the phased array antenna panel.

7. The apparatus according to claim 1 , wherein each of said antenna elements comprises either a single-polarization antenna element or a dual-polarization antenna element.

8. The apparatus according to claim 7 , wherein said dual-polarization antenna element has a vertical feed and a horizontal feed.

9. The apparatus according to claim 1 , wherein each of said beam former circuits comprises a single-polarization beam former circuit or a dual-polarization beam finder circuit.

10. The apparatus according to claim 1 , wherein each of said beam former circuits comprises an interface circuit implementing one or more serial communication protocols.

11. The apparatus according to claim 10 , wherein said serial communication protocols comprise a serial peripheral interface protocol, an inter-integrated circuit communications protocol, or a daisy chain.

12. The apparatus according to claim 1 , wherein said phased array antenna panel is connected to a controller via a serial bus and said controller utilizes said hard-wired address of each of said beam former circuits to program a plurality of phase and gain values into each of said beam former circuits.

13. A method of communicating with a phased array antenna panel comprising:

setting a plurality of hard-wired addresses for a plurality of beam former circuits mounted on said phased array antenna panel adjacent to a plurality of antenna elements;

coupling one or more radio frequency input/output ports of each of said beam former circuits to each of the adjacent antenna elements; and

coupling each of said plurality of beam former circuits to a controller via a serial bus.

14. The method according to claim 13 , wherein each of said beam former circuits comprises an interface circuit implementing one or more serial communication protocols.

15. The method according to claim 14 , wherein said serial communication protocols comprise one or more of a serial peripheral interface protocol, an inter-integrated circuit communications protocol, or a daisy chain.

16. The method according to claim 13 , wherein said controller utilizes said hard-wired addresses of said beam former circuits to program a plurality of phase and gain values into each of said beam former circuits using said serial bus.

17. The method according to claim 13 , further comprising:

generating a plurality of radio-frequency output signals at said ports when operating in a transmit mode; and

receiving a plurality of radio-frequency input signals at said ports when operating in a receive mode.

18. The method according to claim 13 , wherein said hard-wired addresses of each of said beam former circuits are set during manufacture of the beam former circuits.

19. The method according to claim 13 , wherein said hard-wired addresses are programmed using at least one of fuses and anti-fuses within an integrated circuit implementing the beam former circuits.

20. The method according to claim 13 , wherein said hard-wired addresses are set by tying a number of address pins of each of the beam former circuits to either a supply voltage or a ground potential of the phased array antenna panel.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2025
From: RENESAS ELECTRONICS AMERICA INC.
To: AXIRO SEMICONDUCTOR INC.
Reel/Frame 070864/0142 →
MERGER Recorded Apr 15, 2025
From: INTEGRATED DEVICE TECHNOLOGY, INC.
To: RENESAS ELECTRONICS AMERICA INC.
Reel/Frame 070851/0391 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 5, 2018
From: ZIHIR, SAMET; KANAR, TUMAY; YANDURU, NAVEEN KRISHNA
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 046789/0294 →
Cited By (1)
US 12,438,276