IP Library Granted Patent US 10,404,216
Granted Patent B2
US 10,404,216 · App. 15/887,013 · Granted Sep 3, 2019

RF amplifier linearity enhancement with dynamically adjusted variable load

Inventors: Victor Korol (San Diego, CA); Roberto Aparicio Joo (San Diego, CA); Mohsin Asif (Somerville, MA); Shawn Bawell (Amherst, NH)
Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
H03F1/0205H03F3/19H03F2200/411H03F2200/451
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Quick Facts
Patent No.
US 10,404,216
App. No.
15/887,013
Granted
Sep 3, 2019
Kind
B2
Abstract

An apparatus comprises an amplifier having a predefined linear range and a shunt load. The shunt load may be connected to an output, an input, or between gain stages of the amplifier. An impedance of the shunt load dynamically varies in response to a level of a signal presented at a node formed by interconnection of the shunt load and the amplifier, extending linearity of the amplifier beyond the predefined range.

Claims (26)

1. An apparatus comprising:

an amplifier having a predefined linear range; and

a shunt load circuit connected to an output, an input, or between gain stages of said amplifier, wherein the shunt load circuit sets a predefined load resistance level when a level of a signal presented at a node formed by interconnection of the shunt load circuit and the amplifier is below a predefined value and dynamically varies the load resistance level in response to said level of said signal presented at said node formed by interconnection of the shunt load circuit and the amplifier rising above the predefined value, extending linearity of the amplifier beyond the predefined range.

2. The apparatus according to claim 1 , wherein said shunt load circuit comprises a fixed resistance and a dynamically variable resistance.

3. The apparatus according to claim 2 , wherein said dynamically variable resistance is configured to provide a first resistance value when said level of said signal is within said predefined linear range of said amplifier and dynamically vary toward a second resistance value when said level of said signal exceeds said predefined linear range of said amplifier.

4. The apparatus according to claim 2 , wherein said dynamically variable resistance varies nonlinearly in response to said level of said signal when said level of said signal exceeds said predefined linear range of said amplifier.

5. The apparatus according to claim 4 , wherein said nonlinear variation in said dynamically variable resistance counteracts a nonlinear response of said amplifier to an input signal exceeding said predefined linear range of said amplifier.

6. The apparatus according to claim 2 , wherein said dynamically variable resistance varies linearly in response to said level of said signal when said level of said signal exceeds said predefined linear range of said amplifier.

7. The apparatus according to claim 6 , wherein said linear variation in said dynamically variable resistance counteracts a response of said amplifier to an input signal exceeding said predefined linear range of said amplifier.

8. The apparatus according to claim 1 , wherein said amplifier comprises a radio frequency amplifier.

9. The apparatus according to claim 1 , wherein:

said amplifier comprises a first amplifier stage connected to a second amplifier stage; and

said shunt load circuit is connected between said first and said second amplifier stages.

10. The apparatus according to claim 1 , wherein said shunt load circuit comprises a transistor connected in series with a constant current source and a node formed by connection of said transistor and said constant current source is coupled to said output or said input of said amplifier or said gain stages by a capacitor.

11. The apparatus according to claim 1 , wherein said shunt load circuit comprises a transistor connected in series with a constant current source and a node formed by connection of said transistor and said constant current source is coupled to said output or said input of said amplifier or said gain stages by a capacitor in series with a fixed value resistor.

12. A method of extending amplifier gain linearity comprising:

coupling a shunt load circuit to an output or an input of an amplifier stage, said amplifier having a predefined linear range;

maintaining a load resistance level of said shunt load circuit at a first value when a level of a signal at a node formed by interconnection of said shunt load circuit and said amplifier is within said predefined linear range of said amplifier; and

dynamically varying said load resistance level of said shunt load toward a second value when said level of said signal at said node exceeds said predefined linear range of said amplifier.

13. The method according to claim 12 , wherein said shunt load circuit comprises a fixed resistance and a dynamically variable resistance.

14. The method according to claim 13 , wherein said dynamically variable resistance varies nonlinearly in response to said level of said signal when said level of said signal exceeds said predefined linear range of said amplifier.

15. The method according to claim 14 , wherein said nonlinear variation in said dynamically variable resistance counteracts a nonlinear response of said amplifier to an input signal exceeding said predefined linear range of said amplifier.

16. The method according to claim 13 , wherein said dynamically variable resistance varies linearly in response to said level of said signal when said level of said signal exceeds said predefined linear range of said amplifier.

17. The method according to claim 12 , wherein said shunt load circuit comprises a transistor connected in series with a constant current source and a node formed by connection of said transistor and said constant current source is coupled to said output or said input of said amplifier stage by a capacitor.

18. The method according to claim 12 , wherein said shunt load circuit comprises a transistor connected in series with a constant current source and a node formed by connection of said transistor and said constant current source is coupled to said output or said input of said amplifier stage by a capacitor in series with a fixed value resistor.

19. The method according to claim 18 , wherein said fixed value resistor determines said first value of said load resistance level of said shunt load circuit when said level of said signal at said node formed by interconnection of said shunt load circuit and said amplifier is within said predefined linear range of said amplifier.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Jan 15, 2026
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 073487/0395 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2025
From: RENESAS ELECTRONICS AMERICA INC.
To: AXIRO SEMICONDUCTOR INC.
Reel/Frame 070864/0142 →
MERGER Recorded Apr 15, 2025
From: INTEGRATED DEVICE TECHNOLOGY, INC.
To: RENESAS ELECTRONICS AMERICA INC.
Reel/Frame 070851/0391 →
SECURITY INTEREST Recorded May 21, 2018
From: INTEGRATED DEVICE TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 045860/0784 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 2, 2018
From: KOROL, VICTOR; JOO, ROBERTO APARICIO; ASIF, MOHSIN; BAWELL, SHAWN
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 044813/0439 →
Continuity (2)
Provisional Application 62550807 · Aug 28, 2017
Related Publication 20190068121A1 · Feb 28, 2019
Cited By (1)
US 12,500,550