IP Library Granted Patent US 8,902,765
Granted Patent B1
US 8,902,765 · App. 12/712,560 · Granted Dec 2, 2014

Method and apparatus for congestion and fault management with time-to-live

Inventors: Chi-Lie Wang (Milpitas, CA); Jason Z Mo (Fremont, CA)
Assignee: Integrated Device Technology, Inc.
H04L47/286
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,902,765
App. No.
12/712,560
Granted
Dec 2, 2014
Kind
B1
Abstract

A method and apparatus for congestion and fault management with time-to-live (TTL) have been disclosed. Each time a packet is transferred into an Egress Port's Final Buffer, an associated TTL Timeout Counter will be loaded with a value. If the packet cannot be transferred out of the Egress Port before TTL timeout, it will be purged by removing a memory buffer pointer from the corresponding Virtual Output Queue (VOQ) entry.

Claims (1)

1. A method comprising setting a pre-determined time-to-live interval in each packet while said each packet is being written into an egress port's final buffer, and wherein a time-to-live timer for each of said each packet starts at end of packet for said each packet when received by said egress port's final buffer, and wherein said time-to-live interval is based upon a lapsed time, and wherein said each time-to-live timer uses a clock tick to determine when said each time-to-live timer has reached a time-to-live timeout and when said each time-to-live timeout has occurred then for each of said each packet said each packet is discarded through said egress port.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2025
From: RENESAS ELECTRONICS AMERICA INC.
To: AXIRO SEMICONDUCTOR INC.
Reel/Frame 070864/0142 →
MERGER Recorded Apr 15, 2025
From: INTEGRATED DEVICE TECHNOLOGY, INC.
To: RENESAS ELECTRONICS AMERICA INC.
Reel/Frame 070851/0391 →
RELEASE OF SECURITY INTEREST Recorded Mar 29, 2019
From: JPMORGAN CHASE BANK, N.A.
To: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; CHIPX, INCORPORATED; ENDWAVE CORPORATION; MAGNUM SEMICONDUCTOR, INC.
Reel/Frame 048746/0001 →
SECURITY AGREEMENT Recorded Apr 5, 2017
From: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; MAGNUM SEMICONDUCTOR, INC.; ENDWAVE CORPORATION; CHIPX, INCORPORATED
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 042166/0431 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 25, 2010
From: WANG, CHI-LIE; MO, JASON Z
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 023991/0939 →