Scalable coherent apparatus and method

1. A transaction identification mapping for coherent RapidIO memory transactions between a plurality of external hardware processing elements comprising:

for a Request Class Packet Type 2 encoding the 8-bit srcTID (source transaction identification) as a combination of bits from a 4-bit AXI ID (advanced extensible interface identification) and an 8-bit AXI ID; and

for a Response Class Packet Type 13 decoding the targetTID (target transaction identification) into a combination of bits for a 4-bit AXI ID and an 8-bit AXI ID.

2. The transaction identification mapping of claim 1 wherein said decoding the targetTID into a combination of bits for a 4-bit AXI ID and an 8-bit AXI ID comprises the following mapping:

targetTID bit 0 becomes 8-bit AXI ID bit 7 ;

targetTID bit 1 becomes 8-bit AXI ID bit 6 ;

targetTID bit 2 becomes 8-bit AXI ID bit 5 ;

targetTID bit 3 becomes 8-bit AXI ID bit 4 ;

targetTID bit 4 becomes 4-bit AXI ID bit 3 ;

targetTID bit 5 becomes 4-bit AXI ID bit 2 ;

targetTID bit 6 becomes 4-bit AXI ID bit 1 ;

targetTID bit 7 becomes 4-bit AXI ID bit 0 ; and

wherein

4-bit AXI ID bit 3 becomes 8-bit AXI ID bit 3 ;

4-bit AXI ID bit 2 becomes 8-bit AXI ID bit 2 ;

4-bit AXI ID bit 1 becomes 8-bit AXI ID bit 1 ;

4-bit AXI ID bit 0 becomes 8-bit AXI ID bit 0 .

3. The transaction identification mapping of claim 1 wherein said encoding the 8-bit srcTID as a combination of bits from a 4-bit AXI ID and an 8-bit AXI ID comprises the following mapping:

8-bit AXI ID bit 7 becomes srcTID bit 0 ;

8-bit AXI ID bit 6 becomes srcTID bit 1 ;

8-bit AXI ID bit 5 becomes srcTID bit 2 ;

8-bit AXI ID bit 4 becomes srcTID bit 3 ;

4-bit AXI ID bit 3 becomes srcTID bit 4 ;

4-bit AXI ID bit 2 becomes srcTID bit 5 ;

4-bit AXI ID bit 1 becomes srcTID bit 6 ; and

4-bit AXI ID bit 0 becomes srcTID bit 7 .

4. The transaction identification mapping of claim 1 further comprising:

mapping the lowest 3-bits from a 4-bit QoS (quality of service) to a 3-bit RapidIO tuple <CRF, PRIO> (critical request flow, priority).

5. The transaction identification mapping of claim 1 wherein the 4-bit QoS is a 4-bit ARQoS (read address channel quality of service) on a read address channel.

6. The transaction identification mapping of claim 1 wherein the 4-bit QoS is a 4-bit AWQoS (write address channel quality of service) on a write address channel.

7. The transaction identification mapping of claim 5 wherein the 4-bit QoS is a 4-bit AWQoS on a write address channel.

8. The transaction identification mapping of claim 7 wherein the 4-bit QoS to a 3-bit RapidIO tuple <CRF, PRIO> is as follows where AxQoS (AxQoS denotes either the ARQoS (read) or AWQoS (write) as is appropriate to the operation being performed) is selected from the group consisting of ARQoS and AWQoS:

AxQoS of 0000 becomes PRIO of 00 and CRF of 0;

AxQoS of 0001 becomes PRIO of 01 and CRF of 0;

AxQoS of 0010 becomes PRIO of 10 and CRF of 0; and

AxQoS of 0011 becomes PRIO of 11 and CRF of 0.

9. The transaction identification mapping of claim 7 wherein the 4-bit QoS to a 3-bit RapidIO tuple <CRF, PRIO> is as follows where AxQoS is selected from the group consisting of ARQoS and AWQoS:

AxQoS of 0000 becomes PRIO of 00 and CRF of 0;

AxQoS of 0001 becomes PRIO of 00 and CRF of 1;

AxQoS of 0010 becomes PRIO of 01 and CRF of 0;

AxQoS of 0011 becomes PRIO of 01 and CRF of 1;

AxQoS of 0100 becomes PRIO of 10 and CRF of 0;

AxQoS of 0101 becomes PRIO of 10 and CRF of 1;

AxQoS of 0110 becomes PRIO of 11 and CRF of 0; and

AxQoS of 0111 becomes PRIO of 11 and CRF of 1.