Methods and apparatuses for flexible and high performance digital signal processing

1. A Signal Processing Engine (SPE), comprising:

a process input;

a forward delay chain operably coupled between a forward data input and a forward data output and configured for generating a selectable forward tap;

a reverse delay chain operably coupled between a reverse data input and a reverse data output and configured for generating a selectable reverse tap;

a coefficient buffer configured for circulating coefficients within the coefficient buffer and generating a coefficient output;

an add/subtract unit configured for adding or subtracting the selectable forward tap and the selectable reverse tap to generate an intermediate output;

a multiply unit configured to multiply the intermediate output and the coefficient output to generate a multiply result and further configured to bypass, add, or subtract the multiply result with the process input to generate a process output; and

an output delay chain comprising a plurality of serially connected shift registers operably coupled between the process output and a clock delayed process output, the output delay chain including a programmable length.

2. The SPE of claim 1 , wherein the SPE is configured for operable coupling with a plurality of other SPEs by operably coupling at least one of:

the forward delay chain of the SPE to a forward delay chain of at least one of the plurality of other SPEs;

the reverse delay chain of the SPE to a reverse delay chain of at least one of the plurality of other SPEs; and

the process input of the SPE to a process output of at least one of the plurality of other SPEs.

3. The SPE of claim 1 , further comprising an additional forward delay chain, an additional reverse delay chain, an additional add/subtract unit, an additional multiply unit, and an additional output delay chain to form a complex SPE configured for supporting a real data path and an imaginary data path.

4. The SPE of claim 1 , wherein the forward delay chain further comprises:

a plurality of serially connected shift registers with the forward data input operably coupled to a first shift register in the forward delay chain and the forward data output operably coupled to a last shift register in the forward delay chain;

a multiplexer with inputs operably coupled to outputs of the plurality of serially connected shift registers and an output operably coupled to the selectable forward tap; and

a counter operably coupled to the multiplexer and configured for selecting an input of the multiplexer responsive to a desired count value of the counter.

5. The SPE of claim 1 , wherein the reverse delay chain further comprises:

a plurality of serially connected shift registers with the reverse data input operably coupled to a first shift register in the reverse delay chain and the reverse data output operably coupled to a last shift register in the reverse delay chain;

a multiplexer with inputs operably coupled to outputs of the plurality of serially connected shift registers and an output operably coupled to the selectable reverse tap; and

a counter operably coupled to the multiplexer and configured for selecting an input of the multiplexer responsive to a desired count value of the counter.

6. The SPE of claim 1 , wherein the coefficient buffer further comprises a plurality of serially connected shift registers operably coupled as a circular buffer and the coefficient output is operably coupled to an output of one of the plurality of serially connected shift registers.

7. A Signal Processing Engine (SPE), comprising:

a process input;

a forward delay chain operably coupled between a forward data input and a forward data output and configured for generating a selectable forward tap;

a reverse delay chain operably coupled between a reverse data input and a reverse data output and configured for generating a selectable reverse tap;

a coefficient buffer configured for circulating coefficients within the coefficient buffer and generating a coefficient output;

a first bypassable pipeline register for selectively adding a pipeline delay to the selectable forward tap to generate a first addend;

a second bypassable pipeline register for selectively adding a pipeline delay to the selectable reverse tap to generate a second addend;

an adder/subtractor for adding or subtracting the first addend and the second addend to generate a result;

a third bypassable pipeline register for selectively adding a pipeline delay to the result to generate an intermediate output;

a multiply unit configured to multiply the intermediate output and the coefficient output to generate a multiply result and further configured to bypass, add, or subtract the multiply result with the process input to generate a process output; and

an output delay chain configured for generating a delayed process output as a clock delayed version of the process output.

8. The SPE of claim 7 , wherein the add/subtract unit further comprises a multiplexer operably coupled between the adder/subtractor and the third bypassable pipeline register for selecting the first addend, the second addend, the result, or a zero value for an input to the third bypassable pipeline register.

9. A Signal Processing Engine (SPE), comprising:

a process input;

a forward delay chain operably coupled between a forward data input and a forward data output and configured for generating a selectable forward tap;

a reverse delay chain operably coupled between a reverse data input and a reverse data output and configured for generating a selectable reverse tap;

a coefficient buffer configured for circulating coefficients within the coefficient buffer and generating a coefficient output;

an add/subtract unit configured for adding or subtracting the selectable forward tap and the selectable reverse tap to generate an intermediate output;

a multiplier for multiplying the intermediate output and the coefficient output to generate a multiply result;

one or more bypassable pipeline registers for selectively adding pipeline delays to the multiply result;

an adder/subtractor for adding or subtracting the multiply result and the process input to generate an accumulator result;

an output bypassable pipeline register for selectively adding a pipeline delay to the accumulator result to generate a process output; and

an output delay chain configured for generating a delayed process output as a clock delayed version of the process output.

10. The SPE of claim 9 , wherein the multiply unit further comprises a multiplexer operably coupled between the accumulator result and the adder/subtractor for selectively presenting the accumulator result, the process input, or a zero value to the adder/subtractor for arithmetic combination with the multiply result.

11. The SPE of claim 9 , wherein the output delay chain further comprises a plurality of serially connected shift registers with a programmable length wherein the process output is operably coupled to an input of a first shift register in the output delay chain and the clock delayed version of the process output is operably coupled to an output of a last shift register in the output delay chain.

12. A programmable logic array, comprising:

a plurality of programmable logic blocks configured to be programmable for a variety of interconnections and a variety of functions; and

a Signal Processing Engine (SPE), operably coupled to at least some of the plurality of programmable logic blocks, the SPE comprising:

a clock divider configured for dividing down a clock input to supply selectable independent divisor values for a delay chain clock, a coefficient clock, and a multiply clock;

a forward delay chain operably coupled to the delay chain clock and between a forward data input and a forward data output and configured for generating a selectable forward tap at a rate of the coefficient clock;

a reverse delay chain operably coupled to the delay chain clock and between a reverse data input and a reverse data output and configured for generating a selectable reverse tap at a rate of the coefficient clock;

a coefficient buffer operably coupled to the coefficient clock and configured for circulating coefficients within the coefficient buffer and generating a coefficient output;

an add/subtract unit operably coupled to the coefficient clock and configured for adding or subtracting the selectable forward tap and the selectable reverse tap to generate an intermediate output;

a multiply unit operably coupled to the multiply clock and configured to multiply the intermediate output and the coefficient output to generate a process output; and

an output delay chain operably coupled to the multiply clock and the process output and configured for generating a delayed process output.

13. The programmable logic array of claim 12 , wherein the clock divider further comprises:

a clock divider chain for generating a plurality of clocks at a plurality of frequencies;

a first multiplexer for selecting one of the plurality of clocks as the delay chain clock;

a second multiplexer for selecting one of the plurality of clocks as the coefficient clock; and

a third multiplexer for selecting one of the plurality of clocks as the multiply clock.

14. The programmable logic array of claim 12 , further comprising a programmable routing block operably coupled between the SPE and the plurality of programmable logic blocks, the programmable routing block configured to:

correlate data input rates between the plurality of programmable logic blocks and the SPE;

correlate data output rates between the plurality of programmable logic blocks and the SPE; and

provide enhanced routing between the SPE and one or more additional SPEs.

15. The programmable logic array of claim 12 , wherein the add/subtract unit further comprises:

a first bypassable pipeline register for selectively adding a pipeline delay to the selectable forward tap to generate a first addend;

a second bypassable pipeline register for selectively adding a pipeline delay to the selectable reverse tap to generate a second addend;

an adder/subtractor for adding or subtracting the first addend and the second addend to generate a result; and

a third bypassable pipeline register for selectively adding a pipeline delay to the reslt to generate the intermediate output.

16. The programmable logic array of claim 15 , wherein the add/subtract unit further comprises a multiplexer operably coupled between the adder/subtractor and the third bypassable pipeline register for selecting the first addend, the second addend, the result, or a zero value for an input to the third bypassable pipeline register.

17. The programmable logic array of claim 12 , wherein the multiply unit further comprises:

a multiplier for multiplying the intermediate output and the coefficient output to generate a multiply result;

one or more bypassable pipeline registers for selectively adding pipeline delays to the multiply result;

a multiplexer for selectively presenting an accumulator result, a process input, or a zero value on a multiplexer output;

an adder/subtractor for adding or subtracting the multiply result and the multiplexer output to generate the accumulator result; and

an output bypassable pipeline register for selectively adding a pipeline delay to the accumulator result to generate the process output.

18. The programmable logic array of claim 12 , wherein the forward delay chain further comprises:

a plurality of serially connected shift registers with the forward data input operably coupled to a first shift register in the forward delay chain and the forward data output operably coupled to a last shift register in the forward delay chain;

a multiplexer with inputs operably coupled to outputs of the plurality of serially connected shift registers and an output operably coupled to the selectable forward tap; and

a counter operably coupled to the multiplexer and configured for selecting an input of the multiplexer responsive to a desired count value of the counter.

19. The programmable logic array of claim 12 , wherein the reverse delay chain further comprises:

a plurality of serially connected shift registers with the reverse data input operably coupled to a first shift register in the reverse delay chain and the reverse data output operably coupled to a last shift register in the reverse delay chain;

a multiplexer with inputs operably coupled to outputs of the plurality of serially connected shift registers and an output operably coupled to the selectable reverse tap; and

a counter operably coupled to the multiplexer and configured for selecting an input of the multiplexer responsive to a desired count value of the counter.

20. The programmable logic array of claim 12 , wherein the coefficient buffer further comprises a plurality of serially connected shift registers operably coupled as a circular buffer and the coefficient output is operably coupled to an output of one of the plurality of serially connected shift registers.

21. The programmable logic array of claim 12 , wherein the output delay chain further comprises a plurality of serially connected shift registers with a programmable length wherein the process output is operably coupled to an input of a first shift register in the output delay chain and the delayed process output is operably coupled to an output of a last shift register in the output delay chain.

22. A method, comprising:

generating a selectable forward tap with a forward delay amount between a forward data input and a forward data output of a forward delay chain;

generating a selectable reverse tap with a reverse delay amount between a reverse data input and a reverse data output of a reverse delay chain;

generating a coefficient output from a coefficient buffer configured for circulating coefficients;

adding or subtracting the selectable forward tap and the selectable reverse tap to generate an intermediate output;

multiplying the intermediate output and the coefficient output to generate a multiply result;

combining the multiply result and a process input by bypassing, adding, or subtracting the process input with the multiply result to generate an accumulator result; and

delaying the accumulator result by a programmable number of clock cycles to generate a process output by shifting the accumulator result through a plurality of serially connected shift registers with the process output operably coupled to one shift register of the plurality.

23. The method of claim 22 , further comprising operably coupling:

the forward delay chain to a forward delay chain of at least one of a plurality of Signal Processing Engines (SPEs);

the reverse delay chain to a reverse delay chain of at least one of the plurality of SPEs; and

the process input to at least one process output of the plurality of SPEs.

24. The method of claim 22 , further comprising:

correlating data input rates between a plurality of programmable logic blocks and a Signal Processing Engine (SPE);

correlating data output rates between the plurality of programmable logic blocks and the SPE; and

providing enhanced routing between the SPE and one or more additional SPEs.

25. The method of claim 22 , further comprising:

forming an additional data path for performing complex arithmetic using a real data path and an imaginary data path by:

generating an additional selectable forward tap with an additional forward delay amount between an additional forward data input and an additional forward data output of an additional forward delay chain;

generating an additional selectable reverse tap with an additional reverse delay amount between an additional reverse data input and an additional reverse data output of an additional reverse delay chain;

generating an additional coefficient output from an additional coefficient buffer configured for circulating coefficients;

adding or subtracting the additional selectable forward tap and the additional selectable reverse tap to generate an additional intermediate output;

multiplying the additional intermediate output and the additional coefficient output to generate an additional multiply result;

combining the additional multiply result and an additional process input by bypassing, adding, or subtracting the additional process input with the additional multiply result to generate an additional accumulator result; and

delaying the additional accumulator result by the programmable number of clock cycles to generate an additional process output.

26. The method of claim 22 , wherein generating the selectable forward tap further comprises:

shifting the forward data input through a plurality of serially connected shift registers with the forward data output operably coupled to a last shift register of the plurality;

counting to a desired count value; and

selecting an output of one shift register of the plurality as the selectable forward tap responsive to the desired count value.

27. The method of claim 22 , wherein generating the selectable reverse tap further comprises:

shifting the reverse data input through a plurality of serially connected shift registers with the reverse data output operably coupled to a last shift register of the plurality;

counting to a desired count value; and

selecting an output of one shift register of the plurality as the selectable reverse tap responsive to the desired count value.

28. The method of claim 22 , wherein generating the coefficient output further comprises:

re-circulating a plurality of coefficients in the coefficient buffer; and

operably coupling one coefficient of the plurality to the coefficient output.

29. A method, comprising:

generating a selectable forward tap with a forward delay amount between a forward data input and a forward data output of a forward delay chain;

generating a selectable reverse tap with a reverse delay amount between a reverse data input and a reverse data output of a reverse delay chain;

generating a coefficient output from a coefficient buffer configured for circulating coefficients;

selectively adding a pipeline delay to the selectable forward tap to generate a first addend;

selectively adding a pipeline delay to the selectable reverse tap to generate a second addend;

adding or subtracting the first addend and the second addend to generate a result;

selectively adding a pipeline delay to the result to generate an intermediate output;

multiplying the intermediate output and the coefficient output to generate a multiply result;

combining the multiply result and a process input by bypassing, adding, or subtracting the process input with the multiply result to generate an accumulator result; and

delaying the accumulator result by a programmable number of clock cycles to generate a process output.

30. The method of claim 29 , wherein the adding or subtracting the selectable forward tap and the selectable reverse tap further comprises selecting the first addend, the second addend, the result, or a zero value as an input to the act of selectively adding a pipeline delay to the result to generate the intermediate output.

31. The method of claim 29 , wherein delaying the accumulator result further comprises shifting the accumulator result through a plurality of serially connected shift registers with the process output operably coupled to one shift register of the plurality.

32. A method, comprising:

generating a selectable forward tap with a forward delay amount between a forward data input and a forward data output of a forward delay chain;

generating a selectable reverse tap with a reverse delay amount between a reverse data input and a reverse data output of a reverse delay chain;

generating a coefficient output from a coefficient buffer configured for circulating coefficients;

adding or subtracting the selectable forward tap and the selectable reverse tap to generate an intermediate output;

selectively adding pipeline delays to the multiply result;

selectively adding a pipeline delay to the accumulator result to generate the process output;

combining the multiply result and a process input by bypassing, adding, or subtracting the process input with the multiply result to generate an accumulator result; and

delaying the accumulator result by a programmable number of clock cycles to generate a process output.

33. The method of claim 32 , wherein the multiplying further comprises selectively presenting the accumulator result, the process input, or a zero value as another addend to the multiply result in the act of combining.