Clock generation circuits using jitter attenuation control circuits with dynamic range shifting

1. An apparatus comprising:

a phase locked loop (PLL) circuit configured to generate a PLL output signal from an oscillator signal and controlled based on a control signal applied to a control input of the PLL circuit; and

an adaptive control circuit configured to generate a measure of a difference between an input clock signal and the PLL output signal and to apply an offset to the measure to generate the control signal, wherein the offset varies based on a relationship of the measure to a reference, wherein the adaptive control circuit is configured to generate the measure at a greater rate than an update rate of the offset.

2. The apparatus of claim 1 , wherein the PLL circuit comprises a fractional-N PLL circuit comprising a feedback divider that varies responsive to the control signal.

3. The apparatus of claim 2 , wherein the adaptive control circuit comprises:

a control circuit configured to generate a first control signal responsive to the input clock signal and the PLL output signal; and

a dynamic range shifter circuit configured to determine a relationship of the first control signal to a reference, to generate a second control signal from the first control signal and the determined relationship and to apply the second control signal to the control input of the PLL circuit.

4. The apparatus of claim 3 , wherein the dynamic range shifter circuit is configured to shift a dynamic range of an output of the control circuit with respect to the control input of the PLL circuit.

5. The apparatus of claim 3 :

wherein the control circuit comprises an analog-to-digital (ADC) circuit configured to generate the first control signal; and

wherein the dynamic range shifter circuit is configured to increment and decrement an offset signal responsive to the first control signal and to combine the first control signal and the offset signal to generate the second control signal.

6. The apparatus of claim 5 , wherein the ADC circuit is configured to update the first control signal at a first rate and wherein the dynamic range shifter circuit is configured to update the offset signal at a second rate less than the first rate.

7. The apparatus of claim 5 , wherein the control circuit further comprises:

a phase detector and charge pump circuit; and

a loop filter circuit having an input coupled to an output of the phase detector and charge pump circuit and an output coupled to an input of the ADC circuit.

8. The apparatus of claim 1 , further comprising an oscillator configured to generate the oscillator signal, and wherein at least the oscillator and the PLL circuit are implemented in the same single integrated circuit chip.

9. The apparatus of claim 8 , wherein the oscillator comprises a MEMS oscillator.

10. An integrated circuit chip comprising:

an oscillator configured to produce an oscillator signal;

a fractional-N phase locked loop (PLL) configured to generate a PLL output signal from the oscillator signal;

a control circuit configured to receive an input clock signal and the PLL output signal and comprising an analog-to-digital converter (ADC) circuit configured to generate a first control signal responsive to a difference between the input clock signal and the PLL output signal; and

a dynamic range shifter circuit coupling an output of the ADC circuit to a feedback divider control input of the fractional-N PLL circuit and configured to generate a second control signal from the first control signal, wherein the dynamic range shifter circuit is configured shift a dynamic range of the first control signal with respect to the feedback divider control input responsive to a comparison of the first control signal to a reference.

11. The integrated circuit chip of claim 10 , wherein the oscillator comprises a MEMS oscillator.