IP Library Granted Patent US 7,587,131
Granted Patent B1
US 7,587,131 · App. 10/856,436 · Granted Sep 8, 2009

Audio clocking in video applications

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Quick Facts
Patent No.
US 7,587,131
App. No.
10/856,436
Granted
Sep 8, 2009
Kind
B1
Abstract

A method of operating an electronic video device such as a DVD player, wherein video clock signals and audio clock signals are derived from a system clock signal using two phase-lock loops, and these video and audio clock signals are used to process encoded video data and encoded audio data, but digital-to-analog conversion of the audio data stream is controlled by the system clock signal rather than the audio clock signals. By using the system clock signal to control the audio digital-to-analog converter (DAC), the DAC avoids the poor performance issues that can arise from the jitter introduced into the audio clock signals by the PLL. The system clock signal may be divided by an integer to generate the sampling clock for the audio DAC. In the illustrative embodiment, the system clock signal has a rate which is not an integer multiple of the sample rate of the audio data stream. For example, the system clock rate might be 27 MHz while the sample rate of the audio data stream is 44.1 kHz. More generally, the system clock signal preferably has a rate of 108/N MHz, where N is an integer. A sample rate conversion unit in the audio DAC is used to convert the sample rate of the audio data stream to the rate of the system clock signal.

Claims (14)

1. A method of operating an electronic video device, comprising:

generating a system clock signal;

deriving one or more video clock signals from the system clock signal using a first phase-lock loop;

deriving one or more audio processing clock signals from the system clock signal using a second phase-lock loop;

deriving an audio converter clock signal from the system clock signal using a frequency divider;

processing encoded video data to generate a video data stream sampled at a video sample rate using a video processing unit controlled by the one or more video clock signals;

processing encoded audio data to generate an audio data stream sampled at an audio sample rate using an audio processing unit controlled by the one or more audio processing clock signals;

converting the video data stream into video output using a first digital-to-analog converter controlled by the one or more video clock signals; and

converting the audio data stream into audio output using a second digital-to-analog converter controlled by the audio converter clock signal, wherein the frequency of the audio converter clock signal is a non-integer multiple of the audio sample rate.

2. The method of claim 1 wherein the audio converter clock signal has a frequency equal to the frequency of the system clock signal multiplied by N/M, where N and M are integers.

3. The method of claim 1 wherein said step of deriving the one or more audio processing clock signals derives an audio master clock signal and an audio sample signal, the system clock signal having a rate which is not an integer multiple of a rate of the audio sample signal.

4. The method of claim 1 wherein the audio converter clock signal has a frequency equal to 27 MHz multiplied by N/M, where N and M are integers and M is less than or equal to 16.

5. The method of claim 1 wherein the audio converter clock signal has a frequency equal to 54 MHz multiplied by N/M, where N and M are integers and M is less than or equal to 32.

6. The method of claim 1 wherein the audio converter clock signal has a frequency equal to 108 MHz multiplied by N/M, where N and M are integers and M is less than or equal to 64.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Mar 29, 2019
From: JPMORGAN CHASE BANK, N.A.
To: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; CHIPX, INCORPORATED; ENDWAVE CORPORATION; MAGNUM SEMICONDUCTOR, INC.
Reel/Frame 048746/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 4, 2017
From: MAGNUM SEMICONDUCTOR, INC.
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 043207/0637 →
SECURITY AGREEMENT Recorded Apr 5, 2017
From: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; MAGNUM SEMICONDUCTOR, INC.; ENDWAVE CORPORATION; CHIPX, INCORPORATED
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 042166/0431 →
RELEASE OF SECURITY INTEREST Recorded Apr 5, 2017
From: SILICON VALLEY BANK
To: MAGNUM SEMICONDUCTOR, INC.
Reel/Frame 042166/0405 →
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2016
From: CAPITAL IP INVESTMENT PARTNERS LLC
To: MAGNUM SEMICONDUCTOR, INC.
Reel/Frame 038440/0565 →
SECURITY AGREEMENT Recorded Apr 6, 2016
From: MAGNUM SEMICONDUCTOR, INC.
To: SILICON VALLEY BANK
Reel/Frame 038366/0098 →
SHORT-FORM PATENT SECURITY AGREEMENT Recorded Oct 31, 2014
From: MAGNUM SEMICONDUCTOR, INC.
To: CAPITAL IP INVESTMENT PARTNERS LLC, AS ADMINISTRATIVE AGENT
Reel/Frame 034114/0102 →