Automated clock relationship detection
View Patent ↗Automated clock relationship detection may quickly and reliably detect a clock relationship with minimal latency while reducing problems due to metastability occurring at a solitary instant or extended over multiple clock periods. Automated clock relationship detection between two clocks may comprise (a) a shift register synchronizer that reduces the possibility of metastability while capturing and temporarily storing samples of the first clock in response to cycles of the second clock and (b) an evaluator that processes the samples to determine the relationship. A clock relationship detector may also determine the relationship of two clocks by arbitrating a plurality of preliminary determinations of the relationship. Delays may be applied so that each of several detectors receives a clock at a different time, which may avoid metastability in the majority of detectors. The relationship may be used to reliably determine an operating mode of logic driven by one of the clocks.
1. A clock relationship detector to determine a relationship between a first clock and a second clock, the clock relationship detector comprising:
a shift register synchronizer configured to capture and shift a plurality of samples of the first clock in response to cycles of the second clock; and
an evaluator configured to process at least two samples from the plurality of samples to determine the relationship, wherein the relationship comprises relative clock speed indicating a frequency of the first clock relative to a frequency of the second clock or vice versa.
2. The clock relationship detector in accordance with claim 1 , wherein the first clock frequency is less than or equal to the second clock frequency.
3. The clock relationship detector in accordance with claim 2 , wherein clock relationship detector is configured to detect whether the second clock frequency is one or two times the first clock frequency.
4. The clock relationship detector in accordance with claim 3 , wherein the evaluator comprises an exclusive-or (XOR) gate.
5. The clock relationship detector in accordance with claim 1 , wherein the shift register synchronizer is configured to capture and shift a plurality of samples of the first clock in response to each rising edge of the second clock.
6. The clock relationship detector in accordance with claim 1 , wherein the clock relationship detector is configured to shift each of the at least two samples processed by the evaluator at least once.
7. The clock relationship detector in accordance with claim 1 , wherein the clock relationship detector is configured to shift each of the at least two samples processed by the evaluator a different number of times.
8. The clock relationship detector in accordance with claim 1 , wherein the clock relationship detector is configured so that the at least two samples processed by the evaluator are captured by the shift register synchronizer during consecutive cycles of the second clock.
9. The clock relationship detector in accordance with claim 1 , further comprising:
a locker configured to lock the relationship determined by the evaluator after a predetermined number of cycles of the second clock.
10. A clock relationship detector to determine a relationship between a first clock and a second clock, the clock relationship detector comprising:
a plurality of preliminary detectors, each configured to receive and preliminarily determine a relationship between the first and second clocks; and
an arbiter configured to process the preliminary relationship determinations to finally determine the relationship between the first and second clocks.
11. The clock relationship detector in accordance with claim 10 , wherein the clock relationship detector is configured with at least one delay to cause each preliminary detector to receive the first clock at a different time.
12. The clock relationship detector in accordance with claim 11 , wherein the second clock is received by: (a) a first preliminary detector after a first delay, (b) a second preliminary detector after a second delay and (c) a third preliminary detector without delay.
13. The clock relationship detector in accordance with claim 12 , wherein the arbiter finally determines the relationship to match a majority of the preliminarily determined relationships.
14. The clock relationship detector in accordance with claim 10 , wherein each of the plurality of preliminary detectors are identical.
15. The clock relationship detector in accordance with claim 10 , wherein each preliminary detector comprises:
a shift register synchronizer configured to capture and shift a plurality of samples of the first clock in response to cycles of the second clock; and
an evaluator configured to process at least two samples from the plurality of samples to preliminarily determine the relationship.
16. The clock relationship detector in accordance with claim 10 , further comprising:
a locker configured to lock the finally determined relationship after a predetermined number of cycles of the second clock.
17. An electronic device comprising:
first logic in a first clock domain governed by a first clock;
second logic in a second clock domain governed by a second clock; and
a clock relationship detector to determine the relationship between the first and second clocks, the clock relationship detector comprising:
a plurality of preliminary detectors, each configured to receive and preliminarily determine a relationship between the first and second clocks; and
an arbiter configured to process the preliminary relationship determinations to finally determine the relationship between the first and second clocks.
18. The electronic device in accordance with claim 17 , wherein the clock relationship detector is configured with at least one delay to cause each preliminary detector to receive the first clock at a different time.
19. The electronic device in accordance with claim 17 , wherein the clock relationship detector is configured to lock the relationship at a predetermined time.
20. The electronic device in accordance with claim 17 , wherein each preliminary detector comprises:
a shift register synchronizer configured to capture and shift a plurality of samples of the first clock in response to cycles of the second clock; and
an evaluator configured to process at least two samples from the plurality of samples to preliminarily determine the relationship.