IP Library Granted Patent US 9,240,792
Granted Patent B2
US 9,240,792 · App. 14/164,939 · Granted Jan 19, 2016

Monolithic clock generator and timing/frequency reference

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Quick Facts
Patent No.
US 9,240,792
App. No.
14/164,939
Granted
Jan 19, 2016
Kind
B2
Abstract

A periodic signal generator includes a resonant LC tank circuit that generates a periodic reference signal at a first frequency at a differential output thereof. A temperature-responsive frequency compensation module is electrically coupled to the differential output of the resonant LC tank circuit. This module includes a temperature dependent voltage control module that generates a temperature dependent control voltage and an array of switchable capacitive modules that is electrically coupled to a first node of the differential output of the resonant LC tank circuit and responsive to the temperature dependent control voltage and a plurality of switching coefficients. The array of switchable capacitive modules includes a fixed capacitor having a first terminal electrically coupled to the first node and a voltage-controlled variable capacitor having a first terminal electrically coupled to the first node.

Claims (21)

1. A periodic signal generator, comprising:

a resonant LC tank circuit configured to generate a periodic reference signal at a first frequency at a differential output thereof; and

a temperature-responsive frequency compensation module electrically coupled to the differential output of said resonant LC tank circuit, said temperature-responsive frequency compensation module comprising:

first and second arrays of switchable capacitive modules that are electrically coupled to first and second nodes of the differential output of said resonant LC tank circuit, respectively, and responsive to a temperature dependent control voltage and a plurality of switching coefficients; and

a temperature dependent voltage control module configured to generate the temperature dependent control voltage, said temperature dependent voltage control module comprising a temperature dependent current source electrically coupled to a first node of a current mirror and a bank of switchable resistive modules electrically coupled to a second node of the current mirror;

wherein each of the first and second arrays of switchable capacitive modules comprises a respective binary-weighted array of fixed capacitors and a binary-weighted array of voltage-controlled variable capacitors that are responsive to the plurality of switching coefficients;

wherein each of the fixed capacitors in the binary-weighted array of fixed capacitors is associated with a corresponding voltage-controlled variable capacitor in the binary-weighted array of voltage-controlled variable capacitors;

wherein within each of the switchable capacitive modules, either the corresponding fixed capacitor or the corresponding voltage-controlled variable capacitor is active, but not both at the same time; and

wherein when a voltage-controlled variable capacitor is active it has a first terminal responsive to the temperature dependent control voltage and when a voltage-controlled variable capacitor is inactive its first terminal is responsive to a fixed voltage.

2. The periodic signal generator of claim 1 , wherein said temperature dependent voltage control module is configured to generate the temperature dependent control voltage at the second node of the current mirror.

3. The periodic signal generator of claim 1 , wherein each binary-weighted array of voltage-controlled variable capacitors comprises a plurality of inverters having input terminals responsive to the plurality of switching coefficients.

4. The periodic signal generator of claim 3 , wherein each binary-weighted array of voltage-controlled variable capacitors comprises a plurality of pairs of transistors; and wherein the plurality of inverters includes a first inverter having an input terminal electrically coupled to a gate terminal of a first transistor within a first of the plurality of pairs of transistors and an output terminal electrically coupled to a gate terminal of a second transistor within the first of the plurality of pairs of transistors.

5. A periodic signal generator, comprising:

a resonant LC tank circuit configured to generate a periodic reference signal at a first frequency at a differential output thereof; and

a temperature-responsive frequency compensation module electrically coupled to the differential output of said resonant LC tank circuit, said temperature-responsive frequency compensation module comprising:

a temperature dependent voltage control module configured to generate a temperature dependent control voltage; and

an array of switchable capacitive modules electrically coupled to a first node of the differential output of said resonant LC tank circuit and responsive to the temperature dependent control voltage and a plurality of switching coefficients, said array of switchable capacitive modules comprising a fixed capacitor having a first terminal electrically coupled to the first node and a voltage-controlled variable capacitor having a first terminal electrically coupled to the first node;

wherein a second terminal of the fixed capacitor and a second terminal of the voltage-controlled variable capacitor are each responsive to a respective fixed voltage when a corresponding one of the plurality of switching coefficients is in a first logic state; and wherein a second terminal of the voltage-controlled variable capacitor is responsive to the temperature dependent control voltage when the corresponding one of the plurality of switching coefficients is in a second logic state opposite the first logic state.

6. The periodic signal generator of claim 5 , wherein the second terminal of the voltage-controlled variable capacitor is electrically coupled to drain terminals of first and second NMOS pull-down transistors; and wherein a source terminal of the first NMOS pull-down transistor is responsive to the temperature dependent control voltage.

7. The periodic signal generator of claim 6 , further comprising an inverter having input and output terminals electrically connected to a gate terminal of the first NMOS pull-down transistor and a gate terminal of the second NMOS pull-down transistor, respectively, or vice versa.

8. The periodic signal generator of claim 5 , wherein the second terminal of the fixed capacitor is electrically isolated from any fixed voltage when the corresponding one of the plurality of switching coefficients is in the second logic state.

Assignments (2)
RELEASE OF SECURITY INTEREST Recorded Mar 29, 2019
From: JPMORGAN CHASE BANK, N.A.
To: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; CHIPX, INCORPORATED; ENDWAVE CORPORATION; MAGNUM SEMICONDUCTOR, INC.
Reel/Frame 048746/0001 →
SECURITY AGREEMENT Recorded Apr 5, 2017
From: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; MAGNUM SEMICONDUCTOR, INC.; ENDWAVE CORPORATION; CHIPX, INCORPORATED
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 042166/0431 →