Delay-locked loop (DLL) integrated circuits having binary-weighted delay chain units with built-in phase comparators that support efficient phase locking

1. A locked loop integrated circuit, comprising:

a delay chain responsive to a reference clock signal, said delay chain comprising a plurality of delay chain units arranged in ascending or descending order therein; and

a control circuit electrically coupled to said delay chain, said control circuit having a clock generator therein comprising:

a plurality of divide-by-N clock generators responsive to the reference clock signal, said plurality of divide-by-N clock generators having different N values; and

a clock selector electrically coupled to said plurality of divide-by-N clock dividers and configured to select an output of one of the plurality of divide-by-N clock dividers as a control circuit clock, in response a signal generated by said delay chain.

2. A delay-locked loop integrated circuit, comprising:

a delay chain configured to generate a multi-bit delay value signal in response to a reference clock signal; and

a delay chain control circuit electrically coupled to said delay chain, said delay chain control circuit comprising a plurality of clock generators responsive to the reference clock signal and a system clock selector configured to generate an internal clock signal received by said delay chain control circuit in response to a plurality of clock signals generated at outputs of the plurality of clock generators and the multi-bit delay value signal.

3. A delay-locked loop integrated circuit, comprising:

a delay chain configured to generate a multi-bit delay value signal in response to a reference clock signal; and

a delay chain control circuit responsive to the reference clock signal and the multi-bit delay value signal, said delay chain control circuit configured to generate an internal clock signal having a period that is a function of a value of the multi-bit delay value signal.

4. The circuit of claim 3 , wherein said delay chain is further responsive to a multi-bit delay unit enable signal generated by said delay chain control circuit; and wherein said delay chain control circuit is configured to update the multi-bit delay unit enable signal in-sync with the internal clock signal.

5. A method of operating a locked loop integrated circuit, comprising the steps of:

evaluating a plurality of binary-weighted delays provided by a corresponding plurality of delay chain units within a delay chain responsive to a reference clock signal, to thereby identify a first one of the plurality of delay chain units having a first delay in excess of a fraction of a period of the reference clock signal; and

removing a second one of the plurality of delay chain units having a second delay in excess of the first delay from a delay path of the delay chain, in response to identifying the first one of the plurality of delay chain units as having the first delay.

6. The method of claim 5 , further comprising the steps of:

generating a compare signal that identifies a leading or lagging phase relationship between the reference clock signal and a feedback clock signal derived from an output of the delay chain; and

performing a progressive binary search of a lock condition in the locked loop integrated circuit using the compare signal to control adjustments to the delay of the delay chain.

7. A method of operating a locked loop integrated circuit, comprising the steps of:

generating a multi-bit signal that identifies a plurality of delay chain units within a binary-weighted digital delay line that provide a delay greater than one-half a period of a reference clock signal received at an input of the digital delay line; and

setting a delay of the binary-weighted digital delay line to substantially match a delay of a smallest one of the identified plurality of delay chain units.