Method and apparatus for clock generation
View Patent ↗A method and apparatus for clock generation have been disclosed having a selector logic block that controls operation based upon inputs such as analog input(s), digital input(s), a lookup table, and preset value(s), and combinations of such.
1. A clock generator comprising:
a first source of clock parameters having an output;
a second source of clock parameters having an output;
a selection circuit having a first input, a second input, a selection input, and an output, said first input coupled to receive said first source output, said second input coupled to receive said second source output, and said output capable of being coupled to one or more circuits; and
an input capable of receiving an input signal and coupled to said selection input.
2. The clock generator of claim 1 further comprising:
an input capable of receiving an analog signal;
an analog to digital (A/D) converter having an input and an output, said input coupled to receive said analog signal; and
said A/D output coupled to said selection input.
3. The clock generator of claim 1 further comprising:
four or more independent phase lock loops (PLLs) each PLL capable of generating independent clock signals.
4. The clock generator of claim 1 further comprising:
a frequency generation block having a signal input, a feedback input, and an output;
a first divider circuit having an input and an output, said input capable of receiving a reference clock, and said output coupled to said frequency generation block signal input;
a second divider circuit having an input and an output, said input coupled to said frequency generation block signal output, and said output coupled to said frequency generation block signal feedback input; and
a third divider circuit having an input and an output, said input coupled to receive said frequency generation block signal output, and said output capable of being coupled to a destination.
5. The clock generator of claim 4 wherein said one or more circuits are selected from the group consisting of said first divider circuit, said second divider circuit and said third divider circuit.