Patent Assignment
Reel/Frame 042922/0851
Assignment of Assignor's Interest
Recorded: 2017-07-06
Pages: 4
Assignor
INTEGRATED DEVICE TECHNOLOGY, INC.
Executed: 2017-05-31
Assignee
SK HYNIX INC.
2091, GYEONGCHUNG-DAERO, BUBAL-EUB, ICHEON-SI, GYEONGGI-DO, KOREA, REPUBLIC OF
Covered Properties
(7)
Differential Clock Signal Detection Circuit
Circuits and Methods That Attenuate Coupled Noise
Method and Apparatus for Clock Generation
Patent:
7,176,738 →
Application:
10/993,657 →
Integrated Circuits and Methods with Statistics-Based Input Data Signal Sample Timing
Patent:
7,508,893 →
Application:
11/092,032 →
Integrated Circuits and Methods with Transmit-Side Data Bus Deskew
Patent:
7,571,337 →
Application:
11/136,056 →
Method and Apparatus for Clock Generation
Patent:
7,602,226 →
Application:
11/618,545 →
Systems and Methods for Clean Dqs Signal Generation in Source-Synchronous DDR2 Interface Design
Related Assignments
(3)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Apr 26, 2017
From: HWANG, FRANK; YANG, HOWARD; LIEN, CHUEN-DER; LEE, JIMMY
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 042148/0067 →
Security Interest
Jul 25, 2017
From: INTEGRATED DEVICE TECHNOLOGY, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 043095/0414 →
Release of Security Interest
Mar 29, 2019
From: JPMORGAN CHASE BANK, N.A.
To: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; CHIPX, INCORPORATED; ENDWAVE CORPORATION
Reel/Frame 048746/0001 →