Method and apparatus for clock generation
View Patent ↗A method and apparatus for clock generation have been disclosed having a selector logic block that controls operation based upon inputs such as analog input(s), digital input(s), a lookup table, and preset values(s), and combinations of such.
1. A clock chip comprising:
a clock input capable of receiving a reference clock;
an M divider circuit having an input, a control input, and an output, said input coupled to said clock input;
a frequency generation block having a clock input, a feedback input, and an output, said input coupled to said M divider output;
a N divider circuit having an input, a control input, and an output, said input coupled to said frequency generation block output, and said output coupled to said frequency generation block feedback input;
an O divider circuit having an input, a control input, and an output, said input coupled to said frequency generation block output, and said output capable of connection to a destination;
a control logic block having one or more inputs, and one or more outputs, said one or more inputs capable of receiving one or more signals;
one or more sources of information having one or more outputs;
a selector logic block having one or more control inputs, one or more inputs, and one or more outputs, said one or more control inputs coupled to receive said control logic block one or more outputs, and said one or more inputs coupled to receive said one or more sources of information; and
said selector logic block one or more outputs coupled to one or more divider controls selected from the group consisting of said M divider circuit control input, said N divider circuit control input, and said O divider circuit control input.
2. The clock chip of claim 1 wherein said frequency generation block comprises a phase detector, a charge pump, and a controlled oscillator.
3. The clock chip of claim 1 wherein said control logic block one or more inputs are capable of receiving zero or more analog signals, and one or more digital signals.
4. The clock chip of claim 1 wherein said selector logic block further comprises one or more change rate controls in said selector logic block one or more outputs.
5. The clock chip of claim 1 wherein said control logic block further comprises a watchdog timer having one or more inputs, and one or more outputs, said one or more inputs capable of receiving said one or more signals, and said one or more outputs capable of being coupled to one or more reset destinations.
6. The clock chip of claim 1 further comprising four or more frequency generation blocks each such frequency generation block having its own associated M divider, N divider, and O divider.
7. The clock chip of claim 1 wherein said O divider further comprises an output shaping circuit in said O divider output.
8. The clock chip of claim 7 wherein said output shaping circuit is capable or affecting one or more parameters selected from the group consisting of output impedance, overshoot, undershoot, slew rate, delay, skew, and signal strength.