Integrated circuits and methods with statistics-based input data signal sample timing
View Patent ↗An integrated circuit device includes a data input configured to receive a data signal and a clock input configured to receive a clock signal associated with the data signal. The device further includes a sample timing circuit coupled to the clock input and the data input and configured to generate a statistical measure of timing of the data signal and to identify a sample timing for the data signal based on the generated statistical measure. The sample timing circuit may be configured to generate samples of the data signal at a rate higher than a rate of the clock signal, and to generate the statistical measure of timing of the data signal from the data signal samples.
1. An integrated circuit device comprising:
a data input configured to receive a data signal;
a clock input configured to receive a clock signal associated with the data signal; and
a sample timing circuit coupled to the clock input and the data input, the sample timing circuit comprising:
a multiphase clock generator configured to generate a plurality of phased clock signals responsive to the clock signal;
a plurality of latches, respective ones of which are configured to store samples of the data signal responsive to respective ones of the phased clock signals;
a plurality of transition detectors, respective ones of which receive respective pairs of the stored samples corresponding to respective pairs of consecutive edges of the phased clock signals and responsively generate respective transition indication signals;
a plurality of counters that generate respective counts over a plurality of periods of the data signal responsive to respective ones of the transition indication signals;
a count analyzer that generates a sample timing control signal responsive to the counts; and
a data input circuit configured to sample the data signal responsive to the sample timing control signal,
wherein the count analyzer considers transition information from a first number of the plurality of latches to generate the sample timing control signal in a first mode of operation, and wherein the count analyzer considers information from a second number of the plurality of latches to generate the sample timing control signal in a second mode of operation.
2. A device according to claim 1 , wherein the first mode of operation comprises an initialization mode, wherein the second mode of operation comprises a tracking mode, and wherein the first number is less than the second number.