Scan chain registers that utilize feedback paths within latch units to support toggling of latch unit outputs during enhanced delay fault testing
View Patent ↗An integrated circuit device utilizes a serial scan chain register to support efficient reliability testing of internal circuitry that is not readily accessible from the I/O pins of the device. The scan chain register has scan chain latch units that support a toggle mode of operation. The scan chain register is provided with serial and parallel input ports and serial and parallel output ports. Each of the plurality of scan chain latch units includes a latch element and additional circuit elements that are configured to selectively establish a feedback path in the respective latch unit. This feedback path operates to pass an inversion of a signal at an output of the latch to an input of the latch when the corresponding scan chain latch unit is enabled to support a toggle mode of operation.
1. A scan chain register, comprising:
a scan chain latch unit responsive to at least one select signal and a clock signal, said scan chain latch unit configured to support a toggle mode of operation that establishes a next output state of said scan chain latch unit as an invert of a current output state of said scan chain latch unit and further configured to support a freeze mode of operation that establishes the next output state of said scan chain latch unit as equivalent to the current output state of said scan chain latch unit, said scan chain latch unit comprising a multiplexer having four data input terminals and two control terminals that are responsive to a pair of select signals.
2. The scan chain register of claim 1 , wherein said scan chain latch unit is configured to generate a true output state (Q) that is fed back to a first data input of the multiplexer and a complementary output state (QB) that is fed back to a second data input of the multiplexer.
3. The scan chain register of claim 2 , wherein the multiplexer comprises first and second totem pole arrangements of PMOS and NMOS transistors having commonly connected outputs.
4. A scan chain register, comprising:
a scan chain latch unit having serial and parallel input ports and an output port, said scan chain latch unit configured to support at least a pair of freeze and toggle modes of operation that block data at the serial and parallel input ports from influencing CS-to-NS data transitions at the output port, where CS represents a current output state of said scan chain latch unit and NS represents a next output state of said scan chain latch unit; and
wherein said scan chain latch unit comprises a multiplexer having four data input terminals and two control terminals that are responsive to a pair of select signals.
5. The scan chain register of claim 4 , wherein said scan chain latch unit is configured to generate a true output state (Q) that is fed back to a first data input of the multiplexer and a complementary output state (QB) that is fed back to a second data input of the multiplexer.
6. The scan chain register of claim 5 , wherein the multiplexer comprises first and second totem pole arrangements of PMOS and NMOS transistors having commonly connected outputs.
7. A scan chain register, comprising:
a first scan chain latch unit having a first serial input port, a first parallel input port and a first output port, said first scan chain latch unit responsive to a clock signal and configured to support toggle and freeze modes of operation in response to a pair of select signals;
a second scan chain latch unit having a second serial input port, a second parallel input port and a second output port, said second scan chain latch unit responsive to the clock signal and the pair of select signals; and
a dummy flip-flop having a data input electrically coupled to the first output port of said first scan chain latch unit, a clock input responsive to the clock signal and a data output electrically coupled to the second serial input port of said second scan chain latch unit.