IP Library › Granted Patent US 7,564,268
Granted Patent B2
US 7,564,268 · App. 11/557,320 · Granted Jul 21, 2009

Low power logic output buffer

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,564,268
App. No.
11/557,320
Granted
Jul 21, 2009
Kind
B2
Abstract

A low power logic output buffer includes first and second logic gates, each having an input and an output. The input of the first logic gate receives a first logic signal, and the input of the second logic gate receives a second logic signal. The buffer includes first, second, third and fourth n-type metal oxide semiconductor (NMOS). The buffer also includes first and second bias switching NMOS. The first bias switching NMOS is coupled between the source of the third NMOS and ground, and the gate of the first bias switching NMOS is coupled to the output of the first logic gate. The second bias switching NMOS is electrically coupled between the source of the fourth NMOS and ground, and the gate of the second bias switching NMOS is coupled to the output of the second logic gate.

Claims (56)

1. A low power logic output buffer consisting of:

a first logic gate having an input and an output, the input of the first logic gate receiving a first logic signal;

a second logic gate having an input and an output, the input of the second logic gate receiving a second logic signal;

a first buffer output that outputs a first output signal;

a second buffer output that outputs a second output signal;

a first n-type metal oxide semiconductor (NMOS) having a gate, a source and a drain, the source and the drain of the first NMOS being electrically coupled between a rail supply voltage (Vdd 1 ) and a bias to ground, the gate of the first NMOS being electrically coupled to the output of the first logic gate;

a second NMOS having a gate, a source and a drain, the source and the drain of the second NMOS being electrically coupled between the rail supply voltage (Vdd 1 ) and the bias to ground, the gate of the second NMOS being electrically coupled to the output of the second logic gate;

a third NMOS having a gate, a source and a drain, the source and the drain of the third NMOS being electrically coupled between the rail supply voltage (Vdd 1 ) and the first buffer output, the gate of the third NMOS being electrically coupled to the drain of the first NMOS;

a fourth NMOS having a gate, a source and a drain, the source and the drain of the fourth NMOS being electrically coupled between the rail supply voltage (Vdd 1 ) and the second buffer output, the gate of the fourth NMOS being electrically coupled to the drain of the second NMOS;

a first bias switching NMOS having a gate, a source and a drain, the source and the drain of the first bias switching NMOS being electrically coupled between the source of the third NMOS and ground, the gate of the first bias switching NMOS being electrically coupled to the output of the first logic gate;

a second bias switching NMOS having a gate, a source and a drain, the source and the drain of the second bias switching NMOS being electrically coupled between the source of the fourth NMOS and ground, the gate of the second bias switching NMOS being electrically coupled to the output of the second logic gate;

a first bias NMOS having a gate, a source and a drain, the source and the drain of the first bias NMOS being coupled between the first buffer output and the drain of the first bias switching NMOS, the gate of the first bias NMOS being driven by a bias voltage; and

a second bias NMOS having a gate, a source and a drain, the source and the drain of the second bias NMOS being coupled between the second buffer output and the drain of the second bias switching NMOS, the gate of the second bias NMOS being driven by the bias voltage.

2. A low power logic output buffer consisting of:

a first logic gate having an input and an output, the input of the first logic gate receiving a first logic signal;

a second logic gate having an input and an output, the input of the second logic gate receiving a second logic signal;

a first buffer output that outputs a first output signal;

a second buffer output that outputs a second output signal;

a first n-type metal oxide semiconductor (NMOS) having a gate, a source and a drain, the source and the drain of the first NMOS being electrically coupled between a rail supply voltage (Vdd 1 ) and a bias to ground, the gate of the first NMOS being electrically coupled to the output of the first logic gate;

a second NMOS having a gate, a source and a drain, the source and the drain of the second NMOS being electrically coupled between the rail supply voltage (Vdd 1 ) and the bias to ground, the gate of the second NMOS being electrically coupled to the output of the second logic gate;

a third NMOS having a gate, a source and a drain, the source and the drain of the third NMOS being electrically coupled between the rail supply voltage (Vdd 1 ) and the first buffer output, the gate of the third NMOS being electrically coupled to the drain of the first NMOS;

a fourth NMOS having a gate, a source and a drain, the source and the drain of the fourth NMOS being electrically coupled between the rail supply voltage (Vdd 1 ) and the second buffer output, the gate of the fourth NMOS being electrically coupled to the drain of the second NMOS;

a first bias switching NMOS having a gate, a source and a drain, the source and the drain of the first bias switching NMOS being electrically coupled between the source of the third NMOS and generally constant voltage ground, the source of the first bias switching NMOS being directly coupled to generally constant voltage ground, the gate of the first bias switching NMOS being electrically coupled to the output of the first logic gate;

a second bias switching NMOS haying a gate, a source and a drain, the source and the drain of the second bias switching NMOS being electrically coupled between the source of the fourth NMOS and generally constant voltage ground, the source of the first bias switching NMOS being directly coupled to generally constant voltage ground, the gate of the second bias switching NMOS being electrically coupled to the output of the second logic gate;

a first bias resistor coupled between the first buffer output and the drain of the first bias switching NMOS; and

a second bias resistor coupled between the second buffer output and the drain of the second bias switching NMOS.

3. The low power logic output buffer of claim 1 , wherein the low power logic output buffer is formed in an integrated circuit (IC).

4. The low power logic output buffer of claim 1 , wherein the first logic signal and the second logic signal are complementary.

5. The low power logic output buffer of claim 1 , wherein the first logic signal and the second logic signal are clock (CLK) and complementary clock (/CLK).

6. A low power logic output buffer consisting of:

a first logic gate having an input and an output, the input of the first logic gate receiving a first logic signal;

a second logic gate having an input and an output, the input of the second logic gate receiving a second logic signal;

a first buffer output that outputs a first output signal;

a second buffer output that outputs a second output signal;

a first bias switching n-type metal oxide semiconductor (NMOS) having a gate, a source and a drain, the source and the drain of the first bias switching NMOS being electrically coupled between the first buffer output and ground, the source of the first bias switching NMOS being directly connected to ground, the gate of the first bias switching NMOS being electrically coupled to the output of the first logic gate;

a second bias switching NMOS having a gate, a source and a drain, the source and the drain of the second bias switching NMOS being electrically coupled between the second buffer output and ground, the source of the second bias switching NMOS being directly connected to ground, the gate of the second bias switching NMOS being electrically coupled to the output of the second logic gate;

a first bias NMOS having a gate, a source and a drain, the source and the drain of the first bias NMOS being coupled between the first buffer output and the source of the first bias switching NMOS, the gate of the first bias NMOS being driven by a bias voltage; and

a second bias NMOS having a gate, a source and a drain, the source and the drain of the second bias NMOS being coupled between the second buffer output and the source of the second bias switching NMOS, the gate of the second bias NMOS being driven by the bias voltage.

7. A low power logic output buffer consisting of:

a first logic gate having an input and an output, the input of the first logic gate receiving a first logic signal;

a second logic gate having an input and an output, the input of the second logic gate receiving a second logic signal;

a first buffer output that outputs a first output signal;

a second buffer output that outputs a second output signal;

a first bias switching n-type metal oxide semiconductor (NMOS) having a gate, a source and a drain, the source and the drain of the first bias switching NMOS being electrically coupled between the first buffer output and generally constant voltage ground, the source of the first bias switching NMOS being directly connected to generally constant voltage ground, the gate of the first bias switching NMOS being electrically coupled to the output of the first logic gate;

a second bias switching NMOS having a gate, a source and a drain, the source and the drain of the second bias switching NMOS being electrically coupled between the second buffer output and generally constant voltage ground, the source of the second bias switching NMOS being directly connected to generally constant voltage ground, the gate of the second bias switching NMOS being electrically coupled to the output of the second logic gate;

a first bias resistor coupled between the first buffer output and the drain of the first bias switching NMOS; and

a second bias resistor coupled between the second buffer output and the drain of the second bias switching NMOS.

8. The low power logic output buffer of claim 6 , wherein the low power logic output buffer is formed in an integrated circuit (IC).

9. The low power logic output buffer of claim 6 , wherein the first logic signal and the second logic signal are complementary.

10. The low power logic output buffer of claim 6 , wherein the first logic signal and the second logic signal are clock (CLK) and complementary clock (/CLK).

11. The low power logic output buffer of claim 2 , wherein the low power logic output buffer is formed in an integrated circuit (IC).

12. The low power logic output buffer of claim 2 , wherein the first logic signal and the second logic signal are complementary.

13. The low power logic output buffer of claim 2 , wherein the first logic signal and the second logic signal are clock (CLK) and complementary clock (/CLK).

14. The low power logic output buffer of claim 7 , wherein the low power logic output buffer is formed in an integrated circuit (IC).

15. The low power logic output buffer of claim 7 , wherein the first logic signal and the second logic signal are complementary.

16. The low power logic output buffer of claim 7 , wherein the first logic signal and the second logic signal are clock (CLK) and complementary clock (/CLK).

Assignments (3)
RELEASE OF SECURITY INTEREST Recorded Mar 29, 2019
From: JPMORGAN CHASE BANK, N.A.
To: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; CHIPX, INCORPORATED; ENDWAVE CORPORATION; MAGNUM SEMICONDUCTOR, INC.
Reel/Frame 048746/0001 →
SECURITY AGREEMENT Recorded Apr 5, 2017
From: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; MAGNUM SEMICONDUCTOR, INC.; ENDWAVE CORPORATION; CHIPX, INCORPORATED
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 042166/0431 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 7, 2006
From: BUELL, BRIAN J.
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 018491/0659 →