Over driving pin function selection method and circuit

1. A packaged semiconductor device that includes a low voltage memory circuit and a plurality of input pins, the input pins not including pins dedicated to a high-voltage stress test function, the packaged semiconductor device comprising:

an operating voltage input pin for receiving an operating voltage;

a primary function circuit electronically coupled to the operating voltage input pin, the primary function circuit operating at a normal operating voltage range;

a secondary function circuit electronically coupled to the operating voltage input pin, the secondary function circuit for performing a high-voltage stress test on the low voltage memory circuit;

a semaphore signal input pin electronically coupled to the primary function circuit for receiving a signal voltage;

a comparator circuit electronically coupled to the semaphore signal input pin for comparing the signal voltage to the operating voltage, the comparator circuit enabled to disable the primary function circuit and to cause the secondary function circuit to perform the high-voltage stress test on the low voltage memory circuit as long as the signal voltage is greater than the operating voltage; and

a voltage regulator electronically coupled to the operating voltage input pin for providing a voltage lower than the operating voltage to the low voltage memory circuit.

2. The packaged semiconductor device described in claim 1 , wherein the low voltage memory circuit comprises a plurality of dual-port memory cells.

3. The packaged semiconductor device described in claim 1 wherein the secondary function circuit performs a built-in self test of the memory circuit.

4. The packaged semiconductor device described in claim 1 wherein the signal voltage at the semaphore signal input pin must be at least 2 volts higher that the operating voltage to cause the secondary function circuit to perform the high-voltage stress test on the low voltage memory circuit.

5. The packaged semiconductor device described in claim 1 , wherein the operating voltage is a nominal 3.3 volt operating voltage, and wherein the low voltage memory circuit operates on nominally 1.8 volts.

6. For a packaged semiconductor device that includes a package having a fixed number of pins, where none of the pins are dedicated to a test function, the pins including a first semaphore pin that is dedicated to receiving an input signal, the first pin electrically coupled to a first circuit for performing a first function when the input signal is within a normal signal voltage range, a method for adding the test function comprising:

providing a test function circuit in the packaged semiconductor device that performs a dual port memory circuit high-voltage stress test function; and

providing a comparator circuit in the packaged semiconductor device that is electrically coupled to the first semaphore pin, electrically coupled to the first circuit and electrically coupled to the dual port memory circuit high-voltage stress test function circuit, the comparator circuit operable to cause the test function circuit to perform the test function instead of causing the first circuit to perform the first function as long as a voltage at the first semaphore pin has a voltage that is greater than the normal signal voltage range.

7. The packaged semiconductor device described in claim 6 , wherein the normal signal voltage range is the same as a normal operating voltage range for the packaged semiconductor device, the packaged semiconductor device further comprising memory cells enabled to operate at a voltage that is less than the normal operating voltage range.

8. The packaged semiconductor device described in claim 6 , wherein the test function is enabled to test memory cells at a voltage that is greater than a normal operating voltage range.