Signal amplitude distortion within an integrated circuit

1. An integrated circuit comprising:

a serial data transmitter;

a serial data receiver coupled to the serial data transmitter; and

a signal amplitude distorting circuit coupled to the serial data transmitter to distort an amplitude of a serial data signal transmitted from the serial data transmitter to the serial data receiver, wherein the signal amplitude distorting circuit modulates the amplitude of the serial data signal with a waveform pattern controlled by a waveform pattern selecting signal at a frequency controlled by a frequency selecting signal.

2. The integrated circuit of claim 1 , wherein the signal amplitude distorting circuit includes an integrating circuit generating an integrated signal representing an integral of data values output from the serial data transmitter during a preceding interval, the signal amplitude distorting circuit being responsive to the integrated signal to modulate the amplitude of the serial data signal so as to simulate inter-symbol interference with the serial data signal.

3. The integrated circuit of claim 1 , wherein the serial data transmitter comprises:

a current mode logic buffer to generate the serial data signal; and

a bias voltage network to control a total current flow through the current mode logic buffer.

4. The integrated circuit of claim 3 , wherein the amplitude distorting circuit injects a modulated signal into the bias voltage network to distort the amplitude of the serial data signal.

5. The integrated circuit of claim 1 , wherein the waveform pattern is selected from the group consisting of square waveform, triangular waveform, sawtooth waveform and sinusoidal waveform.

6. A method of testing an integrated circuit having a serial data transmitter and a serial data receiver coupled to the serial data transmitter, the method comprising:

distorting an amplitude of a serial data signal at the serial data transmitter, wherein the amplitude of the serial data signal is distorted by modulating the amplitude of the serial data signal with a waveform pattern controlled by a waveform pattern selecting signal at a frequency controlled by a frequency selecting signal and;

transmitting the amplitude distorted serial data signal to the serial data receiver.

7. The method of claim 6 wherein distorting an amplitude of the serial data signal further comprises generating an integrated signal representing an integral of data values output from the serial data transmitter during a preceding interval, and wherein the amplitude is distorted responsive to the integrated signal to modulate the amplitude to simulate inter-symbol interference within the serial data signal.

8. The method of claim 6 further comprising, generating the serial data signal at a current mode logic buffer of the serial data transmitter; and

controlling a total current flow through the current mode logic buffer with a bias voltage network.

9. The method of as claim 8 further comprising, injecting a modulated signal into the bias voltage network so as to distort the amplitude.

10. The integrated circuit of claim 6 , wherein the waveform pattern is selected from the group consisting of square waveform, triangular waveform, sawtooth waveform and sinusoidal waveform.

11. An integrated circuit comprising:

a serial data transmitter that includes a current mode logic buffer and a bias voltage network to control a total current flow through the current mode logic buffer;

a serial data receiver coupled to the serial data transmitter; and

a signal amplitude distorting circuit coupled to the serial data transmitter to distort an amplitude of a serial data signal sent from the serial data transmitter to the serial data receiver, wherein the signal amplitude distorting circuit modulates the amplitude of the serial data signal with a waveform pattern controlled by a waveform pattern selecting signal at a frequency controlled by a frequency selecting signal.

12. The integrated circuit of claim 11 , wherein the signal amplitude distorting circuit includes an integrating circuit generating an integrated signal representing an integral of data values output from the serial data transmitter during a preceding interval, the signal amplitude distorting circuit being responsive to the integrated signal to modulate the amplitude of the serial data signal so as to simulate inter-symbol interference with the serial data signal.

13. The integrated circuit of claim 11 , wherein the amplitude distorting circuit injects a modulated signal into the bias voltage network to distort the amplitude of the serial data signal.

14. The integrated circuit of claim 11 , wherein the waveform pattern is selected from the group consisting of square waveform, triangular waveform, sawtooth waveform and sinusoidal waveform.