Multi-band clock generator with adaptive frequency calibration and enhanced frequency locking

1. A multi-band clock generator, comprising:

a phase-locked loop (PLL) integrated circuit responsive to first and second clock signals, said PLL integrated circuit having a multi-band voltage-controlled oscillator (VCO) therein responsive to a multi-bit control word that selects a frequency sub-band of the VCO; and

an adaptive frequency calibration (AFC) circuit responsive to the first and second clock signals, said AFC circuit configured to look-up an estimate of a target multi-bit control word, which is derived from a previously-determined control word having a value associated with a frequency lock of the multi-band clock generator and stored in a programmable device, during an operation to lock an output clock signal generated by the VCO to a frequency sub-band associated with the target multi-bit control word.

2. The clock generator of claim 1 , wherein the sub-band of the VCO comprises a frequency characteristic curve.

3. The clock generator of claim 1 , wherein the estimate of the target multi-bit control word is the target multi-bit control word.

4. The clock generator of claim 1 , wherein the programmable device comprises at least one register configured to store a multi-bit control word.

5. The clock generator of claim 1 , wherein the programmable device comprises a lookup table having a plurality of programmable entries therein.

6. The clock generator of claim 5 , wherein the first clock signal is a reference clock signal; and wherein said AFC circuit is configured to detect a frequency of the reference clock signal.

7. The clock generator of claim 6 , wherein the second clock signal is a feedback clock signal derived from the output clock signal; and wherein said AFC circuit is configured to detect a frequency of the feedback clock signal and to perform the look-up of the estimate of the target multi-bit control word from within the lookup table based on the frequency difference between the reference clock signal and the feedback clock signal.

8. The clock generator of claim 5 , wherein the programmable entries are derived from simulation results.

9. The clock generator of claim 8 , wherein the simulation results associate each multi-bit control word with a corresponding output clock signal at a VCO tuning voltage.

10. The clock generator of claim 9 , wherein the VCO tuning voltage is determined by a reference voltage.

11. A multi-band clock generator, comprising:

a phase-locked loop (PLL) integrated circuit responsive to first and second clock signals, said PLL integrated circuit having a multi-band voltage-controlled oscillator (VCO) therein responsive to a multi-bit control word that selects a frequency sub-band of the VCO; and

an adaptive frequency calibration (AFC) circuit responsive to the first and second clock signals, said AFC circuit configured to select a first multi-bit control word using a multi-directional jumping algorithm that jumps a plurality of multi-bit control words during an operation to lock an output clock signal generated by the VCO to a frequency sub-band associated with a target multi-bit control word.

12. The clock generator of claim 11 , wherein the multi-directional jumping algorithm selects the first multi-bit control word by jumping to a given point among the plurality of multi-bit control words.

13. The clock generator of claim 12 , wherein the given point is a midpoint among the plurality of multi-bit control words.

14. The clock generator of claim 12 , wherein the given point is determined by a reference voltage.

15. The clock generator of claim 12 , wherein the mufti-directional jumping algorithm ignores multi-bit control words having binary values greater than the first multi-bit control word.

16. The clock generator of claim 12 , wherein the multi-directional jumping algorithm ignores multi-bit control words having binary values smaller than the first multi-bit control word.

17. A multi-band clock generator, comprising:

a phase-locked loop (PLL) integrated circuit responsive to first and second clock signals, said PLL integrated circuit having a multi-band voltage-controlled oscillator (VCO) therein responsive to a multi-bit control word that sets a frequency characteristic curve of the VCO; and

an adaptive frequency calibration (AFC) circuit responsive to the first and second clock signals, said AFC circuit configured to look-up an estimate of a target multi-bit control word, which is derived from a previously-determined lock condition associated with the multi-hand clock generator and stored in a programmable device, during an operation to lock an output clock signal generated by the VCO to a first frequency characteristic curve associated with the target multi-bit control word.

18. The clock generator of claim 17 , wherein the programmable device comprises at least one register configured to store a multi-bit control word.

19. The clock, generator of claim 17 , wherein the programmable device comprises a lookup table having a plurality of programmable entries therein.

20. The clock generator of claim 19 , wherein the first clock signal is a reference clock signal and the second clock signal is a feedback clock signal derived from the output clock signal; and

wherein said AFC circuit is configured to detect a frequency of the reference clock signal and a frequency of the feedback clock signal and to perform the look-up of the estimate of the target multi-bit control word from within the lookup table based on the frequency difference between the reference clock signal and the feedback clock signal.

21. The clock generator of claim 17 , wherein the estimate of the target multi-bit control word is derived from a simulation result stored in the programmable device.