Adaptive reference voltage generators that support high speed signal detection
View Patent ↗An integrated circuit device includes a reference voltage generator, which is configured to generate an adaptive reference voltage (Vref) that varies inversely relative to changes in magnitude of a data signal (DATA) received at an input thereof. This reference voltage generator includes a totem pole arrangement of at least two variable impedance elements having control terminals capacitively coupled (by respective capacitors) to the input. A current mirror is electrically coupled to the totem pole arrangement of at least two variable impedance elements. A comparator is also included. The comparator has a first input terminal that receives the adaptive reference voltage and a second input terminal that receives the data signal.
1. A comparator circuit, comprising:
a reference voltage generator configured to generate an adaptive reference voltage that fluctuates inversely relative to low-to-high and high-to-low changes in a magnitude of a data signal, said reference voltage generator comprising a totem pole arrangement of at least two pairs of matched impedance elements; and
a comparator having a first input terminal configured to receive the adaptive reference voltage and a second input terminal configured to receive the data signal;
wherein a first of the two pairs of matched impedance elements comprise fixed-value resistors and a second of the two pairs of matched impedance elements comprise varistors having magnitudes that fluctuate in opposite directions in response to the low-to-high and high-to-low changes in the magnitude of the data signal.
2. The comparator circuit of claim 1 , wherein said reference voltage generator further comprises a current mirror circuit electrically coupled to the second of the two pair of matched impedance elements.
3. The comparator circuit of claim 2 , wherein a first of the varistors comprises a parallel combination of a first fixed-value resistor and an NMOS transistor and a second of the varistors comprises a parallel combination of a second fixed-value resistor and a PMOS transistor.
4. The comparator circuit of claim 3 , further comprising a pair of sense capacitors electrically coupled across gate terminals of the NMOS and PMOS transistors.
5. The comparator circuit of claim 4 , wherein a common node between the pair of sense capacitors is responsive to the data signal.
6. A comparator circuit, comprising:
a reference voltage generator configured to generate an adaptive reference voltage having a magnitude that varies inversely relative to changes in magnitude of a data signal, which is received at an input of said reference voltage generator; and
a comparator having a first input terminal configured to receive the adaptive reference voltage and a second input terminal configured to receive the data signal.
7. The comparator circuit of claim 6 , wherein said reference voltage generator comprises a totem pole arrangement of at least two variable impedance elements having control terminals capacitively coupled to the input.
8. The comparator circuit of claim 7 , wherein the at least two variable impedance elements include a variable pull-up impedance element and a variable pull-down impedance element, which are commonly connected to an output terminal of said reference voltage generator.
9. The comparator circuit of claim 7 , further comprising a current mirror electrically coupled to said totem pole arrangement of at least two variable impedance elements.
10. The comparator circuit of claim 8 , wherein the totem pole arrangement of at least two variable impedance elements comprises a pair of fixed-value resistors commonly connected to the output terminal.
11. The comparator circuit of claim 8 , wherein a first one of the at least two variable impedance elements is configured as a parallel combination of a fixed-value resistor and a first MOS transistor having a gate terminal capacitively coupled to the input.
12. The comparator circuit of claim 11 , wherein a second one of the at least two variable impedance elements is configured as a parallel combination of a fixed-value resistor and a second MOS transistor having a gate terminal capacitively coupled to the input.
13. The comparator circuit of claim 12 , further comprising:
a first capacitor having a first terminal electrically connected to a gate terminal of the first MOS transistor and a second terminal configured to receive the data signal; and
a second capacitor having a first terminal electrically connected to a gate terminal of the second MOS transistor and a second terminal configured to receive the data signal.
14. The comparator circuit of claim 7 , wherein the totem pole arrangement of at least two variable impedance elements comprises a totem pole arrangement of four fixed-value resistors electrically connected in series.
15. The comparator circuit of claim 14 , wherein the totem pole arrangement of at least two variable impedance elements comprises a PMOS transistor electrically connected in parallel with one of the four fixed-value resistors and an NMOS transistor electrically connected in parallel with another one of the four fixed-value resistors.