Low power output driver
View Patent ↗A low power output driver includes one of a regulated reduced voltage source that receives a supply voltage and outputs a regulated reduced voltage that is a lower voltage than the supply voltage. The driver also includes a first driver input that receives a first logic signal, a second driver input that receives a second logic signal, a first driver output that outputs a first output signal and a second driver output that outputs a second output signal. The driver includes first, second, third and fourth n-type metal oxide semiconductor (NMOS) that are cross-connected between the reduced voltage and the first and second driver outputs or ground. When the second input is high, the second NMOS and the third NMOS are gated on, the second driver output is raised to the reduced voltage and the first driver output is pulled down to the internal ground.
1. A low power output driver system comprising:
(a) a reference voltage supply;
(b) a first voltage regulator that receives reference voltage supply and outputs a first regulated voltage;
(c) a second voltage regulator that receives reference voltage supply and outputs a second regulated voltage;
(d) a first low power output driver; and
(e) a second low power output driver, each of the first and second low power output drivers including:
(i) a first driver input that receives a first logic signal;
(ii) a second driver input that receives a second logic signal;
(iii) a first driver output that outputs a first output signal;
(iv) a second driver output that outputs a second output signal;
(v) a first n-type metal oxide semiconductor (NMOS) having a gate, a source and a drain, the source and the drain of the first NMOS being electrically coupled between the respective first and second regulated voltage and the first driver output, the gate of the first NMOS being electrically coupled to the first driver input;
(vi) a second NMOS having a gate, a source and a drain, the source and the drain of the second NMOS being electrically coupled between the first driver output and an internal ground, the gate of the second NMOS being electrically coupled to the second driver input;
(vii) a third NMOS having a gate, a source and a drain, the source and the drain of the third CMOS being electrically coupled between the respective first and second regulated voltage and the second driver output, the gate of the third NMOS being electrically coupled to the second driver input; and
(viii) a fourth NMOS having a gate, a source and a drain, the source and the drain of the fourth NMOS being electrically coupled between the second driver output and the internal ground, the gate of the fourth NMOS being electrically coupled to the first driver input.
2. The low power output driver system of claim 1 , further comprising:
(f) a third voltage regulator that receives reference voltage supply and outputs a third regulated voltage;
(g) a third low power output driver, the third low power output driver including:
(i) a first driver input that receives the first logic signal;
(ii) a second driver input that receives the second logic signal;
(iii) a first driver output that outputs a first output signal;
(iv) a second driver output that outputs a second output signal;
(v) a first n-type metal oxide semiconductor (NMOS) having a gate, a source and a drain, the source and the drain of the first NMOS being electrically coupled between the third regulated voltage and the first driver output, the gate of the first NMOS being electrically coupled to the first driver input;
(vi) a second NMOS having a gate, a source and a drain, the source and the drain of the second NMOS being electrically coupled between the first driver output and an internal ground, the gate of the second NMOS being electrically coupled to the second driver input;
(vii) a third NMOS having a gate, a source and a drain, the source and the drain of the third CMOS being electrically coupled between the third regulated voltage and the second driver output, the gate of the third NMOS being electrically coupled to the second driver input; and
(viii) a fourth NMOS having a gate, a source and a drain, the source and the drain of the fourth NMOS being electrically coupled between the second driver output and the internal ground, the gate of the fourth NMOS being electrically coupled to the first driver input.
3. The low power output driver system of claim 2 , wherein the first, second and third regulated voltages are different voltage potentials.
4. The low power output driver system of claim 2 , wherein at least two of the first, second and third regulated voltages are approximately the same voltage potential.
5. The low power output driver system of claim 1 , wherein the first and second regulated voltages are different voltage potentials.
6. The low power output driver system of claim 1 , wherein the first and second regulated voltages are approximately the same voltage potential.
7. The low power output driver system of claim 1 , further comprising:
a plurality of low power output drivers coupled to the first voltage regulator; and
a plurality of low power output drivers coupled to the second voltage regulator.