Locked-loop integrated circuits having speed tracking circuits therein
View Patent ↗Clock generators include phase-locked and delay-locked loop integrated circuits that support efficient high speed testing of clock frequencies. An integrated circuit device is provided with a clock signal generator having at least one delay element therein that is responsive to a control signal. A speed tracking circuit is also provided. This speed tracking circuit is configured to generate a signal having a measurable characteristic that tracks changes in a property of the control signal that influences a delay of the at least one delay element.
1. An integrated circuit device, comprising:
a phase-locked loop integrated circuit having at least one delay element therein that is responsive to a control voltage, said phase-locked loop integrated circuit comprising a bias signal generator configured to generate a first bias voltage and a voltage-controlled oscillator responsive to the first bias voltage; and
a speed tracking circuit configured to generate a signal having a measurable characteristic that tracks changes in a property of the control signal that influences a delay of said at least one delay element;
wherein said speed tracking circuit and the bias signal generator are substantially similar circuits.
2. The integrated circuit device of claim 1 , wherein the bias signal generator is responsive to the control voltage; and wherein said speed tracking circuit is configured to generate a signal that tracks changes in a magnitude of the control voltage.
3. The device of claim 2 , wherein the phase-locked loop integrated circuit further comprises a low pass filter; and wherein the control voltage is generated at an output of the low pass filter.
4. The device of claim 3 , wherein said speed tracking circuit is configured to generate a voltage having a magnitude that is offset from the magnitude of the control voltage.
5. The device of claim 2 , wherein said speed tracking circuit is configured to generate a voltage having a magnitude that is offset from the magnitude of the control voltage.
6. A phase-locked loop integrated circuit, comprising:
a bias signal generator configured to generate a bias voltage in response to at least one control voltage;
a voltage-controlled oscillator configured to generate a clock signal in response to the bias voltage;
a speed tracking circuit configured to receive the at least one control voltage and to generate an output signal having a magnitude that indicates whether or not a frequency of the clock signal is within a target range of acceptable frequencies;
a phase frequency detector configured to generate up and down control signals in response to a reference clock signal and a feedback clock signal;
a first charge pump configured to generate a first pump output signal in response to the up and down control signals; and
a second charge pump configured to generate a second pump output signal in response to the up and down control signals.
7. The phase-locked loop integrated circuit of claim 6 , further comprising a low pass filter configured to generate the at least one control voltage in response to the first pump output signal.
8. The phase-locked loop integrated circuit of claim 7 , wherein said speed tracking circuit is responsive to the at least one control voltage.
9. The phase-locked loop integrated circuit of claim 8 , wherein the output signal generated by said speed tracking circuit is configured to track up and down fluctuations in the bias voltage.
10. A delay-locked loop integrated circuit, comprising:
a bias signal generator configured to generate a bias voltage in response to at least one control voltage;
a voltage-controlled delay line configured to generate an output clock signal in response to the bias voltage and an input clock signal; and
a speed tracking circuit configured to receive the at least one control voltage and to generate an output signal having a magnitude that indicates whether or not a frequency of the output clock signal is within a target range of acceptable frequencies; wherein said speed tracking circuit and the bias signal generator are substantially similar circuits.
11. The delay-locked loop integrated circuit of claim 10 , wherein said speed tracking circuit is responsive to the at least one control voltage.
12. The delay-locked loop integrated circuit of claim 11 , wherein the output signal generated by said speed tracking circuit is configured to track up and down fluctuations in the bias voltage.
13. A phase-locked loop integrated circuit, comprising:
a bias signal generator configured to generate a bias voltage in response to at least one control voltage;
a voltage-controlled oscillator configured to generate a clock signal in response to the bias voltage; and
a speed tracking circuit electrically configured to receive the at least one control voltage and to generate a signal having a measurable characteristic that tracks changes in a property of the at least one control voltage ; wherein said speed tracking circuit and the bias signal generator are substantially similar circuits.