Core clock alignment circuits that utilize clock phase learning operations to achieve accurate clocking of data derived from serial data streams having different relative skews
View Patent ↗Core clock alignment circuits include a serial-in parallel-out (SIPO) data processing circuit, which is configured to generate a plurality of lanes of deserialized data in response to a corresponding plurality of lanes of serialized data. The SIPO data processing circuit is further configured to generate a plurality of recovered clock signals from corresponding ones of the plurality of lanes of serialized data. These recovered clock signals may be out-of-phase relative to each other. The devices also include a plurality of lane FIFOs, which are configured to receive respective ones of the plurality of lanes of deserialized data and respective ones of the plurality of recovered clock signals at write ports thereof. A core clock alignment circuit is provided, which may be electrically coupled to the plurality of lane FIFOs. The core clock alignment circuit is configured to perform clock phase learning operations to generate a core clock in response to detecting a plurality of training state headers received by the plurality of lane FIFOs. This core clock may be provided to read ports of the plurality of lane FIFOs to thereby synchronize FIFO read operations.
1. An integrated circuit device, comprising:
a serial-in parallel-out (SIPO) data processing circuit configured to generate a plurality of lanes of deserialized data in response to a corresponding plurality of lanes of serialized data that are out-of-phase relative to each other and further configured to generate a plurality of recovered clock signals from corresponding ones of the plurality of lanes of serialized data;
a plurality of lane FIFOs configured to receive respective ones of the plurality of lanes of deserialized data and respective ones of the plurality of recovered clock signals at write ports thereof; and
a core clock alignment circuit electrically coupled to read ports of said plurality of lane FIFOs, said core clock alignment circuit configured to perform clock phase learning operations to generate a core clock in response to detecting a plurality of training state headers received as data by corresponding ones of said plurality of lane FIFOs and further configured to provide the core clock to the read ports of said plurality of lane FIFOs, said clock phase learning operations comprising:
testing a plurality of out-of-phase core clock candidates that are generated in response to a first one of the plurality of training state headers associated with a first one of the plurality of lanes of serialized data; and
selecting one of the plurality of out-of-phase core clock candidates as the core clock in response to detecting an error during an operation to read data in parallel from all of said plurality of lane FIFOs using another one of the plurality of out-of-phase core clock candidates as a read clock during the operation to read data in parallel from all of said plurality of lane FIFOs.
2. The device of claim 1 , wherein said core clock alignment circuit is configured to generate a plurality of training state header detection signals in response to detecting a corresponding plurality of training state headers received by said plurality of lane FIFOs.
3. The device of claim 2 , wherein said core clock alignment circuit comprises a clock generator that is switched and held in a reset condition in response to a leading edge of one of the plurality of training state header detection signals generated during the clock phase learning operations.
4. The device of claim 3 , wherein said core clock alignment circuit is configured so that the clock generator is switched from the reset condition to an enabled condition in response to a trailing edge of another one of the plurality of training state header detection signals generated during the clock phase learning operations.
5. The device of claim 2 , wherein said core clock alignment circuit comprises a plurality of comparators configured to compare headers received by said plurality of lane FIFOs against a training header stored within the device.
6. The device of claim 3 , wherein the clock generator comprises a divide-by-N counter configured to generate a plurality of phases of a clock signal having a frequency equal to 1/N times a frequency of a clock signal received by the clock generator.
7. The device of claim 6 , wherein said core clock alignment circuit is further configured to select, as the core clock, one of the plurality of core clock candidates having a next earlier phase relative to another one of the plurality of core clock candidates having a phase that caused the error during the operation to read data in parallel from said plurality of lane FIFOs.
8. An integrated circuit device, comprising:
a plurality of lane FIFOs; and
a clock alignment circuit electrically coupled to read and write ports of said plurality of lane FIFOs, said core clock alignment circuit configured to perform clock phase learning operations to thereby generate a core clock in response to detecting a plurality of out-of-phase training state headers received as data at the write ports of said plurality of lane FIFOs and further configured to provide the core clock to the read ports of said plurality of lane FIFOs, said clock phase learning operations comprising:
testing a plurality of core clock candidates having unequal phases, said plurality of core clock candidates generated in response to termination of a last one of the plurality of training state headers received by the integrated circuit device during a training phase of operation; and
selecting one of the plurality of core clock candidates as the core clock in response to detecting an error during an operation to read data in parallel from all of said plurality of lane FIFOs, including all lane FIFOs that received a corresponding training state header having a leading phase relative to the last one of the plurality of training state headers.
9. The device of claim 8 , wherein said core clock alignment circuit is configured to generate a plurality of training state header detection signals in response to detecting a corresponding plurality of training state headers received by said plurality of lane FIFOs.
10. The device of claim 9 , wherein said core clock alignment circuit comprises a clock generator that is switched to and held in a reset condition in response to a leading edge of one of the plurality of training state header detection signals generated during the clock phase learning operations.
11. The device of claim 10 , wherein said core clock alignment circuit is configured so that the clock generator is switched from the reset condition to an enabled condition in response to a trailing edge of another one of the plurality of training state header detection signals generated during the clock phase learning operations.
12. The device of claim 9 , wherein said core clock alignment circuit comprises a plurality of comparators configured to compare headers received by said plurality of lane FIFOs against a training header stored within the device.
13. The device of claim 10 , wherein the clock generator comprises a divide-by-N counter configured to generate a plurality of phases of a clock signal having a frequency equal to 1/N times a frequency of a clock signal received by the clock generator.
14. The device of claim 13 , wherein said core clock alignment circuit is further configured to select, as the core clock, one of the plurality of core clock candidates having a next earlier phase relative to another one of the plurality of core clock candidates having a phase that caused the error during the operation to read data in parallel from said plurality of lane FIFOs.