Voltage reference and supply voltage level detector circuits using proportional to absolute temperature cells

1. A circuit comprising:

a plurality of N-channel field effect transistor Proportional To Absolute Temperature (N-PTAT) cells that are connected to a first supply voltage;

a plurality of P-channel field effect transistor Proportional To Absolute Temperature (P-PTAT) cells that are connected to a second supply voltage;

a plurality of P-channel field effect transistor current sources, a respective one of which is connected to a respective one of the N-PTAT cells;

a plurality of N-channel field effect transistor current sources, a respective one of which is connected to a respective one of the P-PTAT cells;

an additional N-channel field effect transistor current source that is connected to at least one of the plurality of N-channel field effect transistor current sources, but is not directly connected to the P-PTAT cells; and

a coupling circuit that connects at least one of the N-PTAT cells to at least one of the P-PTAT cells;

wherein a respective N-PTAT cell comprises a pair of N-channel field effect transistors having source and drain electrodes that are serially connected and gates that are connected to one another and to a source electrode of one of the N-channel field effect transistors;

wherein a respective P-PTAT cell comprises a pair of P-channel field effect transistors having source and drain electrodes that are serially connected and gates that are connected to one another and to a source electrode of one of the P-channel field effect transistors; and

wherein the coupling circuit comprises a field effect transistor having a gate that is connected to the source electrode of an N-channel field effect transistor of one of the N-PTAT cells, having a source that is connected between the serially connected pair of P-channel field effect transistors of one of the P-PTAT cells and having a drain that is connected to the additional N-channel field effect transistor current source.

2. A circuit according to claim 1 further comprising:

an N-channel Complementary To Absolute Temperature (N-CTAT) device that is connected to and/or included in at least one of the N-PTAT cells to provide an N-channel Constant With Temperature (N-CWT) circuit; and

a P-channel Complementary To Absolute Temperature (P-CTAT) device that is connected to and/or included in at least one of the P-PTAT cells to provide a P-channel Constant With Temperature (P-CWT) circuit.

3. A circuit according to claim 2 wherein the N-CTAT device comprises a drain-to-source voltage of one of the N-channel field effect transistors of one of the plurality of N-PTAT cells.

4. A circuit according to claim 2 wherein the P-CTAT device comprises a drain-to-source voltage of a P-channel field effect transistor that is connected to one of the P-PTAT cells.

5. A circuit according to claim 1 further comprising:

a current generator that is connected to at least one of the P-channel current sources.

6. A circuit according to claim 5 further comprising:

a start-up circuit that is connected to the current generator.

7. A circuit according to claim 1 further comprising:

a hysteresis amplifier that is connected to the coupling circuit.

8. A circuit according to claim 1 :

wherein the plurality of N-PTAT cells are cascaded between a first node and the first power supply voltage;

wherein the plurality of P-PTAT cells are cascaded between the second power supply voltage and a second node; and

wherein the coupling circuit is connected between the first node and one of the plurality of P-PTAT cells that is connected to the second node.

9. A circuit according to claim 1 wherein the plurality of N-PTAT cells and the plurality of P-PTAT cells comprise different numbers of N-PTAT and P-PTAT cells.

10. A circuit according to claim 1 wherein a respective P-channel field effect transistor current source comprises a different number of field effect transistors than a respective N-channel field effect transistor current source.

11. A circuit comprising:

a plurality of N-channel field effect transistor Proportional To Absolute Temperature (N-PTAT) cells that are connected to a first supply voltage;

a plurality of P-channel field effect transistor Proportional To Absolute Temperature (P-PTAT) cells that are connected to a second supply voltage;

a plurality of P-channel field effect transistor current sources, a respective one of which is connected to a respective one of the N-PTAT cells;

a plurality of N-channel field effect transistor current sources, a respective one of which is connected to a respective one of the P-PTAT cells; and

a coupling circuit that connects at least one of the N-PTAT cells to at least one of the P-PTAT cells;

wherein a respective N-PTAT cell comprises a pair of N-channel field effect transistors having source and drain electrodes that are serially connected to define a first node therebetween;

wherein a respective P-channel field effect transistor current source comprises a P-channel field effect transistor that is connected to a respective N-PTAT cell to define a second node therebetween, a respective P-channel field effect transistor current source and a respective N-PTAT cell being serially connected between the second supply voltage and a first node of a succeeding one of the respective N-PTAT cells, the gates of a respective pair of N-channel field effect transistors in a respective N-PTAT cell being connected to a respective second node;

wherein a respective P-PTAT cell comprises a pair of P-channel field effect transistors having source and drain electrodes that are serially connected to define a third node therebetween;

wherein a respective N-channel field effect transistor current source comprises an N-channel field effect transistor that is connected to a respective P-PTAT cell to define a fourth node therebetween, a respective N-channel field effect transistor current source and a respective P-PTAT cell being serially connected between the first supply voltage and a third node of a succeeding one of the respective P-PTAT cells, the gates of a respective pair of P-channel field effect transistors in a respective P-PTAT cell being connected to a respective fourth node; and

wherein the coupling circuit comprises a P-channel field effect transistor, having a gate that is connected to the second node that is between the first one of the N-PTAT cells and the associated P-channel field effect transistor current source, having a source that is connected to the third node that is between the pair of P-channel field effect transistors of the first one of the P-PTAT cells and having a drain that defines an output of the coupling circuit.

12. A circuit according to claim 11 further comprising:

an N-channel Complementary To Absolute Temperature (N-CTAT) device that is connected to and/or included in at least one of the N-PTAT cells to provide an N-channel Constant With Temperature (N-CWT) circuit; and

a P-channel Complementary To Absolute Temperature (P-CTAT) device that is connected to and/or included in at least one of the P-PTAT cells to provide a P-channel Constant With Temperature (P-CWT) circuit.

13. A circuit according to claim 12 wherein the N-CTAT device comprises a drain-to-source voltage of one of the N-channel field effect transistors of one of the plurality of N-PTAT cells.

14. A circuit according to claim 12 wherein the P-CTAT device comprises a drain-to-source voltage of a P-channel field effect transistor that is connected to one of the P-PTAT cells.

15. A circuit according to claim 11 further comprising:

a current generator that is connected to at least one of the P-channel current sources.

16. A circuit according to claim 15 further comprising:

a start-up circuit that is connected to the current generator.

17. A circuit according to claim 11 further comprising:

a hysteresis amplifier that is connected to the coupling circuit.

18. A circuit according to claim 11 wherein a last one of the respective N-PTAT cells is connected to the first supply voltage via a field effect transistor such that the field effect transistor, the last one of the respective N-PTAT cells and the associated P-channel field effect transistor current source are serially connected between the second and first supply voltages.

19. A circuit according to claim 11 wherein the plurality of N-PTAT cells and the plurality of P-PTAT cells comprise different numbers of N-PTAT and P-PTAT cells.

20. A circuit according to claim 11 wherein a respective P-channel field effect transistor current source comprises a different number of field effect transistors than a respective N-channel field effect transistor current source.