Equalization system with stabilized peaking gain for a communication system

1. An equalization system that reduces inter-symbol interference in an input signal, the equalization system comprising:

a variable gain amplifier that receives the input signal, the variable gain amplifier scaling the input signal;

a plurality of peaking amplifiers connected in series with the variable gain amplifier, each peaking amplifier selectively adjusting the peaking gain and peaking corner frequency; and

a PTAT bias generator that provides a PTAT bias current to at least one of the peaking amplifiers to maintain a transconductance of the at least one peaking amplifier substantially constant as temperature changes.

2. The equalization system of claim 1 wherein the PTAT bias generator provides a PTAT bias current to each of the peaking amplifiers to maintain a transconductance of each of the peaking amplifiers substantially constant as temperature changes.

3. An equalization system that reduces inter-symbol interference in an input signal, the equalization system comprising:

a variable gain amplifier that receives the input signal, the variable gain amplifier scaling the input signal; and

a plurality of peaking amplifiers connected in series with the variable gain amplifier, each peaking amplifier selectively adjusting the peaking gain and peaking corner frequency; wherein at least one of the peaking amplifiers includes a programmable shunt capacitor array having at least one capacitor path, and wherein each capacitor path includes a variable capacitor and a capacitor switch that each can be selectively controlled to selectively control the capacitance of the each capacitor path.

4. The equalization system of claim 3 wherein each variable capacitor is a varactor.

5. The equalization system of claim 3 wherein each capacitor path includes a resistor that is in series with a bias voltage that is applied to the variable capacitor when the capacitor switch is closed.

6. An equalization system that reduces inter-symbol interference in an input signal, the equalization system comprising:

a variable gain amplifier that receives the input signal, the variable gain amplifier scaling the input signal; and

a plurality of peaking amplifiers connected in series with the variable gain amplifier, each peaking amplifier selectively adjusting the peaking gain and peaking corner frequency; wherein at least one of the peaking amplifiers includes a programmable resistor array having at least one resistor path.

7. An equalization system that reduces inter-symbol interference in an input signal, the equalization system comprising:

a variable gain amplifier that receives the input signal, the variable gain amplifier scaling the input signal; wherein the variable gain amplifier converts the input signal from a PMOS type common mode to an NMOS type common mode signal; and

a plurality of peaking amplifiers connected in series with the variable gain amplifier, each peaking amplifier selectively adjusting the peaking gain and peaking corner frequency.

8. The equalization system of claim 1 wherein the variable gain amplifier adjusts a variable gain with an extended bandwidth of the variable gain amplifier.

9. An equalization system that reduces inter-symbol interference in an input signal, the equalization system comprising:

a variable gain amplifier that receives the input signal, the variable gain amplifier scaling the input signal; wherein the variable gain amplifier includes a pair of folded PMOS transistors, a programmable resistor array, and a shunt capacitor; and

a plurality of peaking amplifiers connected in series with the variable gain amplifier, each peaking amplifier selectively adjusting the peaking gain and peaking corner frequency.

10. An equalization system that reduces inter-symbol interference in an input signal, the equalization system comprising:

a variable gain amplifier that receives the input signal, the variable gain amplifier scaling the input signal;

a peaking amplifier connected in series with the variable gain amplifier, the peaking amplifier including a transducer; and

a PTAT bias generator that provides a PTAT bias current to the peaking amplifier to maintain a transconductance of the transducer substantially constant as temperature changes.

11. The equalization system of claim 10 wherein the peaking amplifier includes a programmable shunt capacitor array having at least one capacitor path, and wherein each capacitor path includes a variable capacitor and a capacitor switch that each can be selectively controlled to selectively control the capacitance of the each capacitor path.

12. The equalization system of claim 11 wherein each capacitor path includes a resistor that is in series with a bias voltage that is applied to the variable capacitor when the capacitor switch is closed.

13. The equalization system of claim 10 the peaking amplifier includes a programmable resistor array having at least one resistor path.

14. The equalization system of claim 10 wherein the variable gain amplifier converts the input signal from a PMOS type common mode to an NMOS type common mode signal.

15. The equalization system of claim 14 wherein the variable gain amplifier adjusts a variable gain with an extended bandwidth of the variable gain amplifier.

16. The equalization system of claim 15 wherein the variable gain amplifier includes a pair of folded PMOS transistors, a programmable resistor array, and a shunt capacitor.

17. A method for reducing inter-symbol interference in an input signal, the method including the steps of:

scaling the input signal with a variable gain amplifier;

selectively adjusting the peaking gain and peaking corner frequency with a plurality of peaking amplifiers connected in series with the variable gain amplifier; and

providing a PTAT bias current to at least one of the peaking amplifiers to maintain a transconductance of the at least one peaking amplifier substantially constant as temperature changes.

18. A method for reducing inter-symbol interference in an input signal, the method including the steps of:

scaling the input signal with a variable gain amplifier; and

selectively adjusting the peaking gain and peaking corner frequency with a plurality of peaking amplifiers connected in series with the variable gain amplifier; wherein the step of selectively adjusting the peaking gain and peaking corner frequency of the input signal includes the step of providing for at least one of the peaking amplifiers (i) a programmable shunt capacitor array having a first capacitor path and a second capacitor path that are connected in parallel, and wherein each capacitor path includes a variable capacitor and a capacitor switch that each can be selectively controlled to selectively control the capacitance of the each capacitor path, and (ii) a programmable resistor array having a first resistor path and a second resistor path that are connected in parallel.

19. The method of claim 18 wherein each capacitor path includes a resistor that is in series with a bias voltage that is applied to the variable capacitor when the capacitor switch is closed.

20. A method for reducing inter-symbol interference in an input signal, the method including the steps of:

scaling the input signal with a variable gain amplifier;

selectively adjusting the peaking gain and peaking corner frequency with a plurality of peaking amplifiers connected in series with the variable gain amplifier; and

converting the input signal from a PMOS type common mode to an NMOS type common mode signal with the variable gain amplifier.

21. The method of claim 17 further comprising the step of adjusting a variable gain an extended bandwidth with the variable gain amplifier.